RTL Design and Verification of a Parameterised FIFO | QuickSilicon | Hardware Design

Checkout the RTL Design course: quicksilicon.in/
The course covers bunch of more interesting problems and high quality explanation videos consisting of microarchitecture design and line-by-line RTL walkthrough.
QuickSilicon's Alpha Bootcamp on "RTL Design and Verification of a parameterised FIFO".
Check out the complete code here: www.edaplaygro...
The video covers:
- Basics of FIFO
- RTL Implementation of a parameterised FIFO
- Simple Testbench to verify the RTL
- Waveform Overview
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[@QuickSilicon]

We recently launched our new hands-on RTL Design course. Check it out here: quicksilicon.in/course/rtl-design/module/events-to-apb/ About the instructor: www.linkedin.com/posts/raulbehl_100daysofrtl-verilog-servingthenextbug-activity-7011579445681491968-4uiQ?

[@soop168]

Such a good course to revise the basics. Much recommended :)

[@janvilunagariya1612]

It is really very well explained . Please post more such videos

[@QuickSilicon]

Thank you! You might be interested to try out our premium RTL Design course available at quicksilicon.in The explanation there follows the same concept plus it is all hands-on!

[@theoryandapplication7197]

thank you sir it is useful

[@scatteringparameters.4167]

Get a mic

[@QuickSilicon]

I agree the audio is quite bad and I did invest in a mic. Checkout our premium RTL Design course at quicksilicon.in.