Simulating Verilog Designs in Quartus and Modelsim using Testbenches - Essential design flow.

[@ivankolesnikov9183]

Hello, I like this video very much, thank you. A little addition from me: in the window "New Test Bench Settings" you can choose how long it should be simulated: "End simulation at ...". So you don't need to break the simulation manually.

[@wilsondanielmachadotoro9280]

Your work is worth gold! I am very grateful for all the information you have shared with us. I have learned a lot. I hope to continue watching your videos, I love your work. Best regards, my friend.

[@dicleaydemirgunluk]

Thank you so much you saved my homework 💕💕

[@AppalachianEdits]

Hi! Trying to use your work to get started simulating FPGA designs. I follow the steps and code in the video exactly, but always get the error "Error (12061): Can't synthesize current design -- Top partition does not contain any logic". Can you help?

[@dexter97_66]

yes, you should set your testbench as a top module first so it can simulate it properly, doing otherwise would error out the tool because the simulator is always looking for a testbench