Simulation, Synthesis and Design methodology in Verilog | #4 | Verilog in Hindi

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Simulation is used to verify the functionality of the digital design that is modeled using HDL like Verilog.For simulation purpose we apply different input stimulus to the design at different time, to check whether the RTL code behaves in intended way or not.
Synthesis is a process in which the digital design that is modeled using HDL is translated into an implementation consisting logic gates.It will just make an optimal design based on the working strategy which we are using and also give the consumption of resources as available
Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar

[@sameeracharyabandihaldasav8374]

Mam please upload all topics with simulation and synthesis of codes using model simulator and quartus prime U r doing great work mam I joined one of the prestigious VLSI training institute but ur quality of teaching is very much great then their's Mam I really thank you for all ur efforts in making one of the best verilog playlist

[@vlsipoint]

Thank you so much Vijayeendra! Verilog coding videos will be uploaded soon. Stay connected ✌✌

[@chtty5498]

Mam eagerly waiting...happy to.learn. ...😌

[@vlsipoint]

Thanks for watching! Next topic Videos will be uploaded soon.

[@hinamalviya9648]

Nice explanation ..

[@vlsipoint]

Thanks for watching!

[@saikumardussa1643]

Very nice explanation Also post verilog basics videos Eagerly waiting

[@vlsipoint]

Hi Saikumar, Thank you so much! I'll be covering the verilog from basic level to advanced level. Stay tuned ✌

[@jyotimane02]

Please explain Implementation in FPGA verilog !!!!!!!!

[@vlsipoint]

okay

[@yogeshrathour6705]

Well explained 💯

[@vlsipoint]

Thanks Yogesh!

[@rhp1234]

Ma'am pls make complete playlist. You are teaching very well.

[@vlsipoint]

Yes, only FSM part is remaining. Next I'm planning for Advance Verilog Playlist. Stay Connected ✌✌

[@nitishchaudhary9372]

thank you so much

[@tusharmatey9904]

NICE

[@dhananjayamte8268]

Where can i get this ppt to study?

[@vlsipoint]

PPTs are available on VLSI POINT website. Do check it, Keep watching ✌✌

[@dhananjayamte8268]

@@vlsipoint Thank you

[@Ankitkumar-qb2zy]

Mam aap kya t flip flop ka code verilog me likh sakte hai?? Kaise??

[@vlsipoint]

Definitely you can write Flip Flop code in verilog in any modeling style( gate level, data flow, behavioral). In my videos I hv already explain d flip flop code. Please go through the videos.