Verilog interview questions for freshers | #2 | VLSI POINT

[@MrPSP-ry1qn]

Finally someone who makes quality content related to vlsi

[@vlsipoint]

Thanks for watching! Stay connected ✌✌

[@yogishmurthy9320]

Mam can you please explain the UVM concept too. It'll be useful

[@harakhnathsahu8280]

Nice Thank you ma'am

[@ganavip8274]

Just super! Please upload system verilog asap

[@rituasthana5195]

More videos like this one to cover majority vlsi topics for interview point of view

[@pankajkumarsawaliya8491]

Thank You ma'am.Plz keep uploading these kind of videos.

[@vlsipoint]

We will

[@nancydimri]

Thank you ma'am , please upload more videos .

[@vlsipoint]

Sure I will

[@tanyasinha5004]

Thank you for inputs👍

[@vlsipoint]

My pleasure✨ Thanks for watching✌

[@sipranjalisethi1344]

Thank you mam🙏

[@vlsipoint]

My pleasure✨ Thanks for watching✌

[@shashiyadavsos5050]

Thank you ma'am 👍

[@vlsipoint]

My pleasure✨ Thanks for watching✌

[@oviya.n1317]

Pls post more videos

[@pavimahi4501]

Hi mam. How to write a code for self checking test bench for full adder please upload any videos mam

[@anandkumar-bd2ru]

Thank u

[@vlsipoint]

My pleasure✨ Thanks for watching✌

[@kavyayendigeri5158]

Ma'am this all 5 videos for freshers?

[@pavimahi4501]

Hi mam. How to write a code for 8:1 mux using 8 bit register

[@shivendrayadav18]

I have Doubted in logical and case equality. I read javapoint website here is different answer in compare ur given ans

[@shubhanand3791]

Little mistake @2:17 .

[@savanshivanagutti8212]

Yes...the task can't return the value... instead it has output arguments

[@amirraj5881]

Next video

[@pushpendranayak3235]

Nice sister... please make any interview questions video in Hindi...becoz in KZbin I search but I don't found any single video

[@vlsipoint]

Sure Pushpendra, I’ll make that. Keep Watching ✌️