SR Latch using NAND Gates: Basics, Circuit, Working, and Truth Table

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[@elifnurkul2917]

i watched a lot of videos on youtube but i only understood the topic through this particular video. sir, thank you; you saved my life.

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[@tarik_official_07]

Thank you sir ...your explanation is amazing I have some doubt in this topic but now...seen your video all doubt are clear ❤❤❤😊

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Systematic playlist ❤️🔥🔥

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[@ChethanSDN]

absolute gold level content

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[@mohithsai2125]

Thanks!

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[@manojkumarchavali7469]

thank you very much sir i have no words to tell you🙏

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[@scitalks8286]

Awesome explanation!

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Your welcome dear🙏

[@Suhaibking91]

This sir Desreves a like

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[@karanbania4449]

Sir, if we change values of both Q & Q' at 4:13 instead of assuming that they are retained, we still get a valid output, or what I mean is we can still justify those values with S=1 and R=1. How is that possible?

[@VAISHNADEVIGECEUG-]

WONDERFUL EXPLANATION SIR

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[@AbhaySingh-dw1qw]

Wow beautifully explained

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[@Anonymous_user0512]

Yes

[@funoverfun5862]

Thank you sir 🙌

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[@muhammadamirkhan6423]

It's clear my concept

[@EngineeringFunda]

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[@rkarthickraja5846]

Thank u sir Now i have clarified..

[@EngineeringFunda]

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[@AbhaySingh-dw1qw]

It means that when ever we take S as 1 and R as 1 we have to keep in mind previous case op

[@wilson7262]

Very good explanation sir

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[@apuravgupta1622]

This cicruit is not a latch it is called a memory element the first condition for having a latch is to have an enable input and it does not satisfy the first condition . Also if anyone have a simulation tool they can check the circuit of flip flops we study online does not work correctly they even change their state when we give a constant value to a clock. So the flip flops circuit we study are not the correct ones. We should always use Master slave configuration for making a flip flop from a latch and the circuit we study are not flip flop they are latches and only SR and D latch exist other flip flop circuit we study does not work at all. So plz provide correct information to the students and keep up the good work.

[@ahmadjaradat3011]

thank you very much sir

[@EngineeringFunda]

Most welcome

[@stucknsolve4875]

Thank you for easy explanation

[@EngineeringFunda]

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[@stucknsolve4875]

@@EngineeringFunda sure, you are doing great.

[@saipavirala7762]

Wonderful explanation sir Thank you

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[@shrutimishra8957]

Thank uhhhhh so much sir 🙏

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[@vipulmaurya2034]

6:51 sir at this time we find at s=0 r=0 because we find at 1,1 state that is memory.

[@muhammadamirkhan6423]

Thank you 😊

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[@shivinwestwood]

3:03 why the output of Q' goes to the upper gate, As the upper state haven't completed first iteration.

[@ryukadesu]

thanks a lot

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@@EngineeringFunda your 12 mins video explains a lot better than my 45 mins lecture ☺️

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Thanks

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Welcome

[@naveencherry5767]

Sir you did it somewt with in 10 mins what my professor couldn't do in 55 mins

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[@vidyavv1756]

Thanku sir

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[@mjain99]

Why s is 1 and r is 1 in this case?

[@MDRDHIVYALAKSHMIT]

Sir here we don't write reset first then set second? Like nor latch ? ... Because you said first reset then set but you changed here as first set then reset...

[@EngineeringFunda]

That is how it is available dear

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Tq sir 💜🫂✨

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👏

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[@SHALOM9021]

What happens when we change both R and S? If those states:S=0 R=1 and S=1 R=0; acting like memory; then if we change both S and R at the same time ; q and q complement should not be change.Otherwise it is not memory.

[@mandrewsvideos]

Why are the outputs presupposed to be different?

[@yugansh06]

sir aapne using NOR gate likh diya sab mai confusion hori hai pls correct

[@EngineeringFunda]

Done and thanks 😊 🙏

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@@EngineeringFunda You are welcome sir 🤗

[@sairadhakrishna3626]

Exaplain level and edge triggred jk flip flop as soon as possible

[@karthikapyla1297]

S=1 and r= 1 is prohibited case

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Thank you ❤

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You're welcome 😊