Stop it with the 25% Rise Time Rule

[@lesterlan422]

Hi Zach, Another great video. Could we also talk about signal termination? Like when to use it, where to put it, and how to design a good termination for a wide range frequency bandwidth. Thanks.

[@ledricelektronika6635]

WOW finally someone explained it all ^^ Could you share excel file with us?

[@robertdixon8238]

Great explanation! Simplest solution is just do it properly! In 2023 there is no excuse to do it any other way!

[@AlunCalvin]

Mr.Zach ! .your parents made u well! .. my regards to them and to you for keeping up the good work started supported by them ad continued by you!

[@thomassorensen7907]

Hi Zach, Just a question in the above example you show very nicely the effect of the impedance mismatch. But here you have your load impedance ZL= 50 ohm. But do we go about it if this load impedance is not available. Lets say you want to connect an uC to an ADC through SPI, I would assume that the ADC dont have an imput impedance given? or is it not relevant because a SPI would have a very "slow" rise time?

[@Zachariah-Peterson]

In modern components SPI can have a rather fast rise time, especially on BGAs with fine pitch and decent drive strength. There is a common example I cite from a TI ASIC with BGA packaging which has rise times on the SPI bus as low as 2 or 3 ns at low load capacitance. The input impedance is the series of the trace impedance and the input capacitance (or load capacitance), which is often a given value in a datasheet. This RC circuit makes up your load impedance (note that the output is taken as a measurement across the capacitor). To see how this arises it helps to take a transfer function perspective: kzbin.info/www/bejne/bITcf4WnbJiAr80

[@thomassorensen7907]

@@Zachariah-Peterson Thank you for the link and very interesting video. Just for clearence....having a capacitive load would normally mean a full reflection, but in case the line is electrically short, this does not happen?

[@Zachariah-Peterson]

​ @thomassorensen7907 This is a good question because in theory no load is purely capacitive. There is always a little bit of resistance leading to a capacitive load. But in the case of a long line the answer is yes, a capacitive load results in a reflection and a signal that travels between the load and source end of the line. We would normally impedance match at the source end to set the input voltage level and simultaneously dampen the reflection so that the voltage settles at the desired level. We could also parallel terminate and get the same result but with no reflection at the load. These parallel and series placements happen internally in compoennts that are designed to a specific standard so that you don't need to manually apply termination unless you intentionally deviate from the required trace impedance. For the short line, the signal exists across the source, load, and trace simultaneously, they all look like a point impedance when taken together.

[@87Spectr]

Fantastic!

[@petersage5157]

Those purple fill lights. What, did you fell into a door again? "Nothing. You've told him twice already."

[@jotnarymir1393]

Yeah sounds a lot easier to use impedance calculator!