SystemVerilog for Verification Session 2 - Basic Data Types (Part 1)

[@rishabhkumarsoni1240]

Wow man, beautiful explanation. I was looking for good content for SV finally found your channel.

[@Ishwakithakkar]

Thanks Kavish for these efforts. Great Concise Information. It was a great help.

[@vasup6607]

Thank you so much for the video... I had the confusion between wire & tri net usage, It got cleared after watching your video, you have explained it very neatly.

[@Fansuri85]

Thank you Kavish, good tutorial with coding practice at the end, well done!

[@rutanshu85]

Great video Kavish...Thanks !

[@naveen7282]

Nice explanation sir, please add more videos and help us !!

[@CairosNaobum]

best sir. please add more. (I'm not Indian but like your lectures. Greetings from Norway. :3)

[@usr_jisa]

You have done a very good job. Thank you very much..!!

[@kavishshah3724]

Please find quiz solutions link in video description.

[@SachidanandBNaragundakar]

HELLO KAVISH PLEASE LET ME KNOW AT 16:49 OUTPUT FOR EXAMPLE OF WIRE/TRI I AM GETTING DATA=Z INSTEAD OF X AS PER UR VIDEO ????

[@uday5786]

is there any book available for this

[@rajaniduba6106]

thank you so much sir...Please make a video for constraints in SV--hard, soft and inline constraints

[@ajaykumargoud7627]

This simulator is very user friendly and very flexible...is there any way that I can use for it to build my career...

[@vaishakhigajera7877]

Add more videos about assertions and coverage.

[@Arunleo.]

in packed and unpacked example u have chanced the name of packed to unpacked in initial block but u have not changed the variable ".w" in display ...i think that ,must also be changed .then you must check?

[@akashashpradhan4107]

gr8 observation but because the error occurs on the assignment line that error was not reported.

[@shahbaazahamad]

Excellent

[@Ramzy993]

i wonder what is the simulator do you use ??? and how can i get it ??

[@akashashpradhan4107]

you should have millions to get the software license of synopsys VCS simulator.

[@javedkhan1984]

nice video....

[@rajkapadia7324]

can you give me access to the solutions?

[@AjayMukeshMehtaMVD]

how to do vcs simulation on windows

[@harshgohel8514]

at 9.45 you changed struct_packed to struct_unpacked but you forgot to change struct_packed into display statement it should be struct_unpacked.q over there in display statement..

[@prathyushad4107]

module abc(); wire a; tri d; logic b1,b2,s; assign a = b1; assign d=s?b1:1'bz; initial begin b1=1'b1; s=1'b1; $display("a=%b",a); $display("d=%b",d); end endmodule im getting a=x and d=x but for you it was a=1 and d=x can you explain me in detail how it was