Free Systemverilog Course : Udemy: VLSI Verification Courses: SV Beginner 2: Lear More TB Constructs

[@mohammedimrankhan6265]

In mailbox explanation end class should be axi driver instead of axi generator.Nice video

[@SystemverilogAcademy]

Yes, that's true. Thanks for the correction & feedback !!

[@vidyagopinath4459]

The subtitles need to be corrected... Ot Nice class sir

[@SystemverilogAcademy]

Thanks for feedback 👍 Subtitles are auto generated and won't be good enough to relay on .

[@alterguy4327]

Thankyou

[@SystemverilogAcademy]

👍

[@SystemverilogAcademy]

Thanks 🙂

[@lixiang7349]

Among * 3 not between.

[@SystemverilogAcademy]

👍

[@alterguy4327]

58:04 Bookmark

[@SystemverilogAcademy]

Its kind of summary for interface usage 👍

[@uday5786]

thank u for video sir.can u please provide the ppt

[@SystemverilogAcademy]

Thanks for the feedback. The materials can't be shared and sorry about that.

[@alterguy4327]

Is this course available in Udemy

[@SystemverilogAcademy]

Any of our course are no more available in Udemy. All in this KZbin channel