Systemverilog generate : Where to use generate statement in Verilog & Systemverilog

[@SandeepKumar-px4kf]

very good explanation

[@ravisoni9645]

Very simple explanation,Thank you so much for your hard work,keep posting more such videos. Thanks alot

[@SystemverilogAcademy]

Thank you for the feedback !

[@harsha9215]

sir, Does modules in generate block will execute concurrently or sequentially? if concurrently how to use generate for interdependent modules.

[@SystemverilogAcademy]

If you 'generate' any block of code (including module), they will be executed in parallel in simulation. (didn't get your second question 😕 )

[@harsha9215]

@@SystemverilogAcademy is there any way to excute module serially

[@tanujsharma6316]

can there be nested generate statements? if yes then what will be the name for the instantiated module

[@SystemverilogAcademy]

It's possible according to the LRM. (Refer "27. Generate constructs" in the 2017 LRM) The instance names will also appear accordingly. Example, parameter SIZE1,SIZE2 = 2; genvar i, j generate for (i=0; i

[@lakshmikanthk442]

Can we use generate block inside the functions, like if we have recursive call?

[@SystemverilogAcademy]

I don't think there is any restriction for the usage of 'generate' inside the function, but always be aware of the use case of 'generate'.

[@noufalnishath1937]

hi, i have tried the same scenario without providing generate block.but still getting output without any error.could please explain me why?

[@SystemverilogAcademy]

If you don't use generate, it will not 'generate' multiple components , it will be just a single circuit component.