TSMC FinFlex: How Chips are made Worse to get Better

[@someasiandude4797]

programmers rather buy a processor that could simulate the entire universe than optimize their code for lower end hardware

[@CamaradaArdi]

Programmers do optimize their code though

[@someasiandude4797]

@@CamaradaArdi i have seen games with no textures have a file size of 5GBs

[@CamaradaArdi]

@@someasiandude4797 code != assets

[@the_expidition427]

RAW files

[@kwonekstrom2138]

@@someasiandude4797LOL. Code usually isn't very big. Sounds like media, data, and support systems.

[@oberguga]

In short words. FinFets allow transistor to grow upward, so manufacturers start to reduce planars surface of transistors, but compensate it by making it taller.

[@oberguga]

Sorry for any grammatic mistakes, KZbin app has some strange bug regarding dark theme so I don't see what I am aI writing right now.

[@teamacio9043]

Tnx

[@rain-uw9ju]

​@@oberguga so it isnt only me 😂

[@JordanCoopersNook]

So what you're saying is eventually processors will just be large grey cubes gotcha

[@GR8APE69]

​@@rain-uw9ju Is it making your cursor jump around as if it's detecting random taps around the screen? Especially when you backspace to fix an error, it'll like jumble the two words together and fuck up a whole sentence? Is that the one you're talking about? Please say yes because I was starting to think the touch sensor in my phone was screwy or that perhaps my screen protector was doing something weird. But I've noticed it really only happens when writing comments in the KZbin app, and I exclusively use the dark theme.

[@AnonyMous-gt8vq]

Let me issue another, very important correction. Using a larger standard cell does NOT enable a higher clock speed. In fact, fore every application the optimal size standard cell is used, which minimizes power consumption. Today, this is calculated automatically, based on standard cell datasheet. The condition used to calculate this is called fan out and is basically to how many standard cell inputs does the output of the previous cell connect. So for more connection a larger cell must be used, otherwise the rise and fall time of the signal will be slow, increasing the switching losses. To control the actual speed of the standard cell, different voltage treshold cells are used. Low treshold cells for example will be faster than high treshold cells. Further there are high and low power cells available, both have then also several different voltage treshold variations. Finally all the different types of cells come in different sizes, so the appropriate size can always be chosen.

[@Gractus]

Thanks for pointing that out. Seems like another important piece of the puzzle for me to understand how processors really work. Feels like I'm getting close to putting it all together.

[@AnonyMous-gt8vq]

@@Gractus Yeah, just want to issue small corrections as an industry insider. So the author, as well as the audience cal learn small details.

[@SINHRO-FAZA]

@@AnonyMous-gt8vq Только вот в закон Мура они давно упёрлись и топчутся на месте, по сути не уменьшая сам транзистор в объёме, он становится своего рода колодцм, который для наблюдателя сверху кажется не большим, НО если посмотреть с боку, он огромен. Давно пора выплюнуть это погоню за уменьшением и развиваться совсем в другом направлении, а именно многоядерности и способности работать нескольким ядрам как одно целое, а не плодить 30-40 ядер и ничтожно низкой производительностью.

[@GR8APE69]

​@@AnonyMous-gt8vq I really appreciate that! It frustrates me when I seek an understanding of something, but people over-analogize it to the point that their explanations get me no closer to a proper understanding of the concept. Like, I'm not an idiot, I'm just ignorant. Give me all of the technical words and concepts and tell me in no uncertain terms exactly how it works, and then if I need an explanation for this or that I can ask for clarification. But you can't ELI5 something this technical and expect whoever you're teaching to have a real understanding of what's going on. It's like reading the Cliff's Notes to a book and then writing an essay about it; to anybody who's read the actual book, it's clear you have only a facile understanding of the story. Am I making sense? I don't want a facile understanding. I'd rather be faced with the fact that something is over my head and simply accept that fact rather than live with the illusion that I understand something more than I actually do. That's how these comment threads attract so many "experts" ready to tell you why they're right.

[@GR8APE69]

​@@SINHRO-FAZA As we like to say here in the US: "Old habits die hard!" It'll be some time yet before these old dogs learn some new tricks. I have more idioms that don't translate well if you'd like to hear them 😅

[@Benis650]

I'm an engineer working in the semiconductor industry, and before clicking on this video, I didn’t have any particular expectations. However, your explanation turned out to be far more comprehensive and easy to understand than I anticipated-truly excellent. You covered everything from the basic semiconductor component structure to logic gates, IC design and layout concepts, and even introduced fundamental semiconductor manufacturing processes. This is a fantastic and impressive introduction to semiconductor manufacturing, perfect for newcomers interested in the industry. Well done

[@HighYield]

Thank you so much. My “trick” is that I have to understand it myself first in order to explain it. And since my original background isn’t in semiconductors, once I understand it, I can explain it to other people without requiring a lot of previous knowledge. It’s basically “semi for dummies” since I’m a dummy myself :p

[@auritro3903]

As a high school teen who is really interested in CPU and transistor design, this channel seems like a perfect start for me and my semiconductor journey. Your explanations are clear, concise and engaging. I would love to see more such videos in the future :)

[@BGTech1]

That’s a great start! Stick with your interests because it can eventually get you a high paying job as an engineer. I’m studying electronics engineering in college right now. My whole life I’ve loved electronics.

[@PhilfreezeCH]

Asianometry is another great one.

[@auritro3903]

@@PhilfreezeCH Yeah, I watch him too :D

[@auritro3903]

@@BGTech1 Yeah, I'm planning to stick with with electronics and engineering for college too, as it is my final year of high school. I have always loved semiconductors and computers, and have seen how companies like Intel, TSMC, NVIDIA, Samsung, AMD etc. have practically revolutionized the tech space. As for you, I'm happy that you also enjoy semiconductors a lot. Good luck to you too!

[@famjsnoek]

Add TechTechPotato also to your list.

[@handlemonium]

You and Asianometry are the best 👍

[@HighYield]

A comparison that honors me!

[@IsleyNumber1]

​@@HighYieldI think you're better - your presentation certainly is

[@salmiakki5638]

​@@HighYieldIt shouldn't, this channel is in another league when covering a given subject. Asianometry has some good videos, and the knowledge of the owner's dad in silicon manufacturing (especially in Taiwan) shines through in those, but others are much more lackluster when he chooses to cover topics outside his field of knowledge

[@salmiakki5638]

If I had to give one, My quality comparison proposal would be with Huygens optics, both outstanding 😊 (although his videos are slightly more academic in tone, I feel, yours more outreach-y, in every good meaning of the term)

[@handlemonium]

@@salmiakki5638 yes many Asianometry vids are more of a general overview while more than a handful of them actually get pretty detailed on semiconductor technologies and the progression of manufacturing processes.

[@spicybaguette7706]

Great explainer! One minor nitpick: CMOS in ICs is not really about creating a transistor from an NMOS and PMOS transistors, it's about using both NMOS and PMOS in a logic gate. CMOS is more power-efficient because it complements PMOS and NMOS circuits in the logic gate, so that pull-up and pull-down resistors are not needed (hence the name).The logic diagram of a NAND gate you showed already visualizes how this works: you have a pull-up circuit (the top one) consisting of two PMOS transistors in parallel, which pull up the output line when either of the input voltages is low. Then you have the pull-down circuit which pulls down the output line when both input voltages are high. Generally, p-type transistors are used in pull-up and n-type in pull-down if I recall correctly, though I don't remember why. Also, larger logic gates are not necessarily used for high performance or higher frequency. Like you said, they provide more current, but they are selected based on multiple criteria. For example the fan-out, which is the amount of logic gates that it needs to power. A larger logic gate consumes more power when switching, which can actually be detrimental at higher clock rates. Different size alternatives of logic gates are selected automatically by EDA software and used interchangeably

[@ILoveTinfoilHats]

(it's because of the voltage curve in nmos and pmos is inverted)

[@bayanzabihiyan7465]

Because Nmos turn on from the “Gate-Source” voltage. If you try to use it to supply positive voltage. The voltage at the source rises to VCC which makes the gate-source delta fall and turn off. So Nmos can’t pass high voltage. But when used on the 0v side, it can easily connect ground to a circuit and drop basically no voltage. Pmos works the opposite, since it level of “on” gets magnified as the voltage on the source terminal increases relative to gate. So you use Pmos on high side, and Nmos on low side.

[@shigaraja]

this is basically the concept of "don't build out, build up." that led to the idea of Skyrises. so instead of taking up more area these transistors are taking up more volume. which will in turn lead to smaller but thicker chips with at least the same performance. it is better optimizations of the space that is already there but ultimately it is still limited as i would assume that there is a physical limit to how high these fins can be before they become too fragile.

[@mariobombo]

This is one of the best explanation of finflex - youtube algorithm should really pick up and spread this video.

[@joechang8696]

a transistor has two properties each with two possible conditions. One is N and P type as you said the other is depletion and enhancement mode. In depletion, the channel is on at zero gate voltage, gate voltage is required to turn on. Enhancement mode, channel is off w/o at 0 gate voltage, and on with

[@HighYield]

True. And you can actually place different cell heights across different rows. Everything is so complex, at some point you have to cut information to keep things from becoming too bloated.

[@NN-gb5lf]

I wrote a longer reply to a different comment on this but on modern digital-focused high-performance nodes, depletion mode devices are no longer a thing. Everything is by default enhancement mode and it won't even be explicitly called out. Depletion mode devices may only be found in mature analog nodes at this point.

[@joechang8696]

@@NN-gb5lf thanks, much has changed since the 90's. I will try to find. is this 1) to help with leakage? 2) deliberate not doping the channel? 3) field effect of the gate shuts off the channel? or other?

[@Jake_Gotthard]

⁠@@HighYieldplease make an occasional “Information dump” video which doesnt Cut ANY information and hell, might even go into extra. That’d be AMAZING for people who really want to Learn the stupidly obscure details!

[@AnonyMous-gt8vq]

Let me just give a small correction to the video. There are two types of transistors, both of p and for n type. They are called enchancement mode and depletion mode transistors. This refers to wether the transistors are on or off for zero gate voltage. For the n mos, enchancement mode transistor, which is described in the video indeed a positive gate voltage is required to open it. For the depletion mode transistor, however, it will be open even at 0 gate voltage. Positive gate voltage will attract even more electrons, opening it more, while negative gate voltage will repel the electrons, closing it. This type of transistor is rare and only used for high frequency analog application. For the p type it is similar. A negative voltage on the gate will attract electron holes, which are positively charged. A positive voltage will repel the holes, closing the transistor. In a depletion mode transistor the holes are already present at zero gate voltage, forming the channel.

[@NN-gb5lf]

While it is true that enhancement and depletion mode transistors absolutely do exist, I think it is important to emphasize that when talking about modern high-performance digital-focused nodes, depletion mode devices are no longer a thing. Every transistor is essentially an enhancement-mode device, to the extent that we designers don't explicitly mention it. There may well be older analog-focused nodes still kicking around that have depletion mode devices but the cost+risk vs benefit for implementing a device like that in modern nodes is far too high.

[@shapedeus]

But there doesn't appear to be any negative voltage (with respect to gnd), only positive vdd and gnd=0. Then how is it possible to attract holes to switch on a p-type transistor?

[@otheraccount5252]

Came here to say this to find your comment already addressing this. Disappointing to see such a basic mistake in what I'd hoped to be a good technical overview video of the subject matter.

[@aretorta]

He also got the charges mixed around: he stated that a negative charge repels the electron holes.

[@nicholasweiss4662]

​@@shapedeus Negative Gate voltage refers to the voltage measured between gate and source of the transistor. P Mos usually have the source at a higher potential than their drain. On N Mos its the other way around. Now lets say a P Mos has its source at 5V and its gate at 4V relative to ground. Then the voltage measured from gate to source is 4V - 5V = -1V, so you get a negative gate-source Voltage (VGS)

[@MFMegaZeroX7]

Yay, a new High Yield video! And thanks for pointing out Ken Sheriff's blog, I'll definitely want to give it a read sometime.

[@devbites77]

I really like your clear and concise teaching style for this complex topic. It was fascinating to hear about the tech. Even though I'm mostly software focused, I have a strong interest in micro-electronics, and circuit design.

[@nviorres]

Amazing video, explaining a complex topic in 25 minutes in a way that someone without and relevant knowledge can understand.

[@Exotic-9780]

Love these in depth videos

[@HighYield]

I posted 30 sec ago, I'm sure you haven't watched it yet ;) But yes, it's pretty in-depth. Hope you enjoy!

[@Drumaier]

I'm constantly reading and watching videos about this topic, just because I'm a little nerd and this nano technology and logic things related to chip manufacturing blows my mind. I try to understand about all this but is too complex and I lack basic education about electricity to start with (I'm just a 3d artist). BUT, this video was different, I'm leaving with the impression of undertanding some things at least. For example I didn't know CMOS meant P and N transistors toguether, didn't know that you can compensate less fins with taller ones....and seeing the animations now I understand better in which direction the current flow (I have it flipped in my head 😅🤡). So, thanks a lot for this video, is really making a big difference for me. I'd love to see more of this videos in which you explain more of this things, a "chip design for dummies" series would be soooo cool.

[@KingofArsenal]

This type of content, is why I fell in love with KZbin, information like this is very rare, so thank you sir, your channel will becomes huge! Just keep this up!

[@zblurth855]

I feel like I should have paid to see something that well explained

[@HighYield]

There’s always my Patreon 😇

[@miinyoo]

Neat! Someone finally clearly explained Cell Height and why transistors are set up in groups rather than individually.

[@ab-lymphocite5464]

There is another benefit to fin depop. Less parasitic capacitance from nearby fins sapping your performance away and increasing power. Also fewer fins means lower leakage (since there is less "transistor" to leak).

[@sage5296]

I mean you say that, but the idea of fin depop is more to keep the total fin surface area the same while decreasing the silicon footprint, compensating for that loss in height, so I think it would have the same levels of parasitic capacitance likely

[@ab-lymphocite5464]

@@sage5296 It’s hard to explain without a whiteboard but you do end up ahead. 2 fins that are 1.5 high vs 3 fins that are 1 high have the same drive area. The area of the capacitor is 1 side (space between fin 1 and 2) times 1.5 height for the two fin situation. For the three fin situation it is 2 sides (space between 1 and 2 and the space between 2 and 3) times 1 height. Therefore all else being equal the 2 fin device will have a 25% capacitance reduction over a 3 fin device with the same drive area. You also get better uniformity because for a one or two fin device all fins will have the same parasitics while for 3+ the inner and outer fins will perform differently despite being part of the same device.

[@Jay-sr8ge]

Love this video. I have a running curiousity how semiconductor chips work and information like this is simple enough to understand and not be overwhelming, yet comples enough to give a great coverage of the concepts

[@CyrusTabery]

Great video. Pelgrom‘s constant and the relation of variable performance and management of transistor variation along with the impact on power performance could be a fun follow up. Thanks so much.

[@zmm978]

The ability to parse such technology into our brain is on itself a remarkable technology, brilliant video Mr. Yield.

[@mahmoodnaderan2131]

Thanks for the video and thanks for introducing the blogs

[@RafaGmod]

omg this video is great!! Loved the summary of concepts and a lot of new information. Didn't knew about the libraries!! This is gold, thank you!

[@ericstromquist9458]

What a great explanation of FinFET scailing! Glad I found your channel. Just watched you GAA video too. Will be looking out for your future videos.

[@HighYield]

I'll try to produce more videos, these 2 month breaks are not what I want. But since it's just a hobby, it's hard to find the time I need for research and writing :(

[@Drew1218s]

7/6nm might’ve been the best node of recent times. We saw large performance and efficiency gains when mobile phone chips went to 7nm and big gains on desktop when amd went to 7nm. 7/6 is still used today and it’s 6+ years old.

[@Olibelus]

You are a master teacher; this video was awesome. Thank you.

[@Phil-D83]

I am still amazed that anything below 22nm is able to fabricated on mass

[@erkinalp]

thank EUV multipatterning

[@mrwpg]

I've always said Moore's Law should be viewed in 3D not 2D...

[@tommihommi1]

moores law was about count, not density

[@mrwpg]

@@tommihommi1 you are a cabbage, Think matrix vs array, they both have a "count". Density is a measure of compactness not a count. Moores law states the number of transistors doubles every two years, nothing mentioned about 2D or 3D, silly cabbages just assume 2D without a single reason. we don't live in flatworld... maybe educate yourself before crying...

[@Winnetou17]

@@tommihommi1 Indirectly it was about density, because the count increase and cost decrease are coming from miniaturization.

[@Maadhawk]

It is the old saying, "an Engineer knows he has achieved perfection not when he has nothing left to add, but rather when he has nothing left to take away." They added what they needed to get it to work. Now they are taking away to perfect it.

[@thomaslai9058]

A designer knows he has achieved perfection not when there is nothing left to add, but when there is nothing left to take away. Antoine de Saint-Exupery

[@SeanBZA]

EDA and foundry are linked, foundry thinks of a thing, makes a few sample chips using hand layout and some dummy wafers, then sees it works, and approaches the EDA companies, who then make the needed software. Only once the software is ready, and can build parts that work, with repeatable performance, will the new process be announced. There must be plenty of process improvements that died a quiet death because the software simply could not make it work and produce a more optimal part layout, so that was shelved till they could get this to work properly, possibly using another process try.

[@kintustis]

interesting title format.

[@HighYield]

Yeah, it plays off the thumbnail. Maybe I'll change it. Let's see how it performs-

[@ronchum5178]

I wonder if we will have a future where peak optimized finfet is the process used for cheaper consumer and budget chips while gate all around will be used for more enterprise and luxury chips. It seems like finfet has staying power by virtue of how much more complex gate all around is going to be.

[@Alfred-Neuman]

I'd be curious to know why they aren't making motherboards with multiple CPU slots just like they do with RAM... That way instead of buying one very expensive CPU we could install 2 or 3 cheap CPUs and get even more performance for a lot cheaper isn't it? I'm supposing it would be feasible because I still have an old DELL Windows 2003 Server that had two CPU slots on the Motherboard.

[@spicybaguette7706]

​​@@Alfred-NeumanIt's because designing a motherboard for multiple CPUs is complicated and probably more expensive than just buying a better CPU. It gets used in servers, because beyond a certain point, it's the only way to add more cores to a system. Like those dual-socket EPYC servers, they are incredibly cool, but more suited for hyperscaler workloads (running dozens of VMs on a system), since software can struggle actually using the available amount of cores So for a giant computer cluster it makes sense, since you need half the number of systems for roughly the same performance, which is much more efficient. But for most consumers, not really

[@AdvantestInc]

The idea of "making a chip better by making it worse" through fin depopulation is both counterintuitive and fascinating, great explanation!

[@andrewhumphries4029]

Even I understood this video! Great work, please do more

[@transcendtient]

Everyone that talks about Moore's Law forgets the part where it is supposed to get cheaper.

[@YoureSoVane]

The same capabilities are getting cheaper, unless you're Texas Instruments and you have a monopoly. The basic digital camera with the same resolution, storage capacity, frame rate, and connectivity as five years ago costs less now than it did back then. It's just that no one wants less capability so nobody buys them, and manufacturers stop making them.

[@ianlogan3055]

This was very informative, thank you.

[@HighYield]

Thank you for watching :)

[@jarretname4837]

excellent video! as others have said, it feels like I should be paying for this quality of content

[@marce.fa28]

You’re by far my favorite KZbinr. 🥰🤙🏼

[@Mondochiwan]

This video has brought me the closest to understand how this dark magic works! Thank you!

[@harrkev]

As to standard cell sizing, they commonly come in multiple sizes. And it isn't just speed, it's also how large the net is that is being driven. That could go to 20 or 30 other inputs, so you want a big beefy driver for that. That. Also, if you have a line that goes a long way you want a bigger driver for that too. But you would use a smaller one for a short Trace that only goes to a couple cells. Modern synthesis and place and route tools. Do this for you. Pretty much automatically. They will size cells up or down as necessary while still meeting the timing.

[@jpwillm5252]

Très bonnes explications. 🔬🤓 Merci !

[@Crisdapari]

From transistor basics to 4nm Kowloon architecture 😂 Quality content!! 👌

[@interrobangings]

YEEEEESSSSS HE UPLOADED

[@N1klas13]

Im a bit of a dummy but I now understand what finflex means. Thanks! I have read a couple of notes in the comments but I have to say further information on behaviour on 0 gate voltage etc. would have made it harder for me to understand. Maybe a bit more accuracy on cmos cells would have made it a bit clearer, but I think it was already pretty obvious that cmos is not actually a third transistor type but a design combining n and p type transistor, especially considering the visual representation. So while I appreciate other people adding further information, I don’t think lack of those details in your video is a valid criticism of your very helpful explanation on the topic, as some few seem to think.

[@user-bz8qi6vu4q]

Nice vid ; learned a lot - thank you

[@anonymouscommentator]

i always love you videos, thank you so much!

[@ChannelSho]

Thanks for pointing out the concept of Standard Cells. Now I get why AMD can't make Zen 4c/5c and get the same characteristics as the normal versions.

[@Nobe_Oddy]

wait... finDePop ??? that was the name of my band in high school HAHA!

[@HighYield]

Technical genius even in high school ;)

[@yiannos3009]

Excellent video!

[@AaronLyNxAI]

I remember watching a video not long ago, where rat neurons are being grown and taught to play doom, technology like this, while morally gray, could potentially help fields of robotics, medicine, astronomy, and anything else that traditional computers can be limited in. The research on this is relatively small but with more time and experiments I believe biological computing could be a reality

[@peterjansen4826]

An addition on why p-mos is on top might be interesting.

[@snake4eva]

@HighYield This video was so informative, great video

[@rahulav4009]

Big fan of yours, thanks for these amazing videos

[@JinKee]

You and Asianometry are my fave chip channels

[@ThatJay283]

<a href="#" class="seekto" data-time="90">1:30</a> correction: with both NPN and PNP transistors, when there is flow of current between base and emitter, current can flow between collector and emitter. so when the transistor is on, current can flow.

[@stickfijibugs]

He is not referring to junction transistors (NPN & PNP). These are field effect transistors (N-channel & P-channel) and behave entirely differently, although I agree that his explanation is very poor.

[@GreyDeathVaccine]

I give you AAA rating for this stellar quality. Thx, bro.

[@justhitreset858]

Fantastic video. Hope to see more

[@briancase6180]

When most people say "semiconductors," they actually mean "integrated circuits." In fact, that's true here too. I don't know when "semiconductors" became equated with "integrated circuits" in the minds of non-industry and now even industry experts, but it happened. I think it's time to, please, reverse this trend. Semiconductors are materials that, well, conduct incompletely or variably. Integrated circuits are made *with* or *of* semiconductors. If you are using transistors, you are creating integrated circuits, not semiconductors. And, there's no such thing as a CMOS transistor; the two complementary transistors used in CMOS make up the most simple *gate.* It's a gate, not a transistor; it's an inverter (probably, unless it's designed simply as a repeater). Oh, and transistors have a gate, which sits across the channel. The channel is a physical structure; it's not "created" when a field is applied to the gate. Sorry, you are pretty good at this, but still not precise.

[@HighYield]

It's also called the semiconductor industry. At some point, you can't reverse a set trend. Yeah, ICs are made with semiconductors, but nowadays these terms are interchangeable.

[@doogong]

This was very informative!!

[@BrandonMeyer1641]

Now I understand what they mean when the guys at Intel said they “doped” the wafers at the gn fab tour.

[@theodoremurdock9984]

I think you missed the point on the power efficiency of cmos…my understanding is that cmos is used because it’s more power efficient than either pmos or nmos alone. If you only use pmos or only use nmos, either a one is represented as power flowing and a zero is represented as power not flowing or vice versa. That means there’s constant current flow and energy loss. If you combine a pmos circuit where power flow represents a 1 with an nmos circuit where power flow represents a zero, you get a circuit where there’s no power flow at all, but if the pmos circuit is open and the nmos circuit is closed, that’s a one, while if the nmos circuit is open but the pmos circuit is blocking the flow, that’s a zero. Instead of representing values by whether power is flowing, you represent values by why the power isn’t flowing (the pmos side or the nmos side), and that’s when you get massive power savings…it’s not that the one kind was much better than the other in terms of power draw, but that putting both together stops a lot of wasted power.

[@Psychx_]

The Cortex A72 core that's used as a pipe cleaner for process testing since the 16nm node would surely hit 5GHz+ by now xD

[@seanjorgenson7251]

Atomera's technology will play a roll in extending Moores law soon especially in the legacy nodes.

[@rikki146]

Nice vid by Mr High Yield! Today is a good day.

[@aasishwarsaravana5748]

All this just shows how complex Chip Manufacturing really is, and how we have optimised to be so powerful and smaller than the human brain, it can power Language Models and give rise to AI! Can you make a Video detailing purely the Chip Imprinting process, ie. How the design is actually being imprinted into silicon wafers to then become cpus? In my opinion, they are a form of ultra advanced 3d printing process for making logic circuits on a nanoscale! I would like to know how does the imprinting lens in an EUV machine work, and how is the imprinter done, like how can we generate a opaque picture that blocks UV light in the form of a pattern, and the remaining light going through the lens imprints the cpu design on the wafer? To me, that in itself is the Most Impressive process of Chip Making!

[@ouulriyac4747]

Awesome video

[@cameramaker]

I would not say that those next-node transistors are *Worse*. They are in all aspects really *Improved* ones (I would not use Optimised, because that bears a negative aspect of a trade-off). So the TLDR from this video is - the next node is not a nanometer size reduction, its the same on X/Y axis. But the Z - height - has grown. So more into what V-nand brought to the SSDs. And the FinFlex is then a further Improvement - combining benefits of both cell types.

[@NootNoot.]

Time to learn! 📝Is the title broken? Do you mean, "[Fin Depopulation] and How It's Used To Make Chips Worse, but Better"? OH, saw your other comment. I think those types of titles plays well inside the thumbnail, while the title of the video is about the topic. Imo, when people look at a video, they read the title first, then if you have text inside the thumbnail, they'll read it as a 2nd sentence or if the title is a rhetorical question, the answer is in the thumbnail

[@HighYield]

Yeah, my thought was ppl read the thumbnail and then the title. But it doesn't see so. I changed it. "[Fin Depopulation] and How It's Used To Make Chips Worse, but Better" also sounds good. Maybe I'll try that if the current title doesn't perform well :)

[@stickfijibugs]

Your videos are superb and well-researched. However, you could use an improvement in your explanation of the field-effect transistor (N-channel & P-channel) at <a href="#" class="seekto" data-time="140">2:20</a>, without complicating it with physics. The key to note is that in any one transistor, the source and drain materials are different even though they are of the same polarity. Therefore you need to provide reference in your explanation. Hence, when the voltage on an NMOS transistor's gate is more positive than its source, the internal electric field created induces conduction between its source and drain, meaning that it is in the ON (or closed) condition. The crux is that when the voltage is the SAME on the gate as the source (eg zero volts difference), it is in the OFF (or open) condition. Conversely, when the voltage on a PMOS transistor's gate is more negative than its source, the internal electric field created induces conduction between its source and drain, meaning that it is in the ON (or closed) condition. The crux is that when the voltage is the SAME on the gate as the source (eg zero volts difference), it is in the OFF (or open) condition. Note this last line is same explanation as for NMOS! Now here's neat thing about all this (look at a schematic of a CMOS inverter). In the simplest case of an inverter logic gate with one PMOS and one NMOS, you connect the gates together for the input, and the drains together for the output. Next, you connect the NMOS source to GND, and the big deal is this: you "flip" the PMOS relative to the NMOS, that is, you connect the PMOS source to +5V. Now, in reference to GND (your voltmeter red probe on the connected drains and black probe on GND), if you apply 0V to the input (ground the gates), note that the NMOS is OFF while the PMOS is ON, so you get +5V on the output (0V input changes to +5V output). Conversely, still referenced to GND, if you apply 5V to the input (connect the gates to +5V), note that now the PMOS is OFF while the NMOS is ON, so you get 0V on the output (+5V input changes to 0V output) ... and there is the inversion. You might ask .. so what is the charm of CMOS??? First of all, CMOS is not a kind-of transistor as he suggests, it is a technology. Fundamentally CMOS technology combines both NMOS and PMOS transistors, pairing functionality such that when one is ON the other is OFF (hence Complementary Metal Oxide Semiconductor, CMOS). The simplest CMOS circuit is the INVERTER. Let's travel back to the early days of CPUs ... Simply put ... back then (early 70's) PMOS transistors were difficult to realize, especially on the same die with NMOS transistors. So instead of using a PMOS transistor in the INVERTER, a resistor was used, tied to +5V, and only an NMOS transistor was used. This was called a "pull-up" resistor. That meant when the NMOS transistor was ON, current had to flow both through the resistor and the NMOS device, HEATING the resistor and wasting power. Moreover, when the NMOS transistor transitioned from its ON to OFF state, the resistor had to charge up tiny capacitors further down line, slowing down the response (RC effect) of the next switching circuit. So it was a double-whammy, HEAT and LOW SPEED, and, it was impossible to overclock those CPUs. Therefore, if an early NMOS-only CPU was stopped but still powered, it would be HOT without doing any work ... that is .. statistically half of its resistors would be conducting and the other half not, in a steady condition. So basically, the heat produced by stopped CPU and a running CPU was not much different! Advent of CMOS. Replacing the pull-up resistor by a PMOS device brought two benefits: 1) as I explained above, when the NMOS was in its ON state, the PMOS would be OFF, hence NO HEAT, and 2) when the NMOS was in its OFF state, the PMOS would be ON, delivering power ONLY to the next stage, not to its NMOS (because it is OFF). Furthermore, the output drive was now "active" instead of "passive", all put together resulted in a dramatic increase in speed and decrease in power dissipation. The first single-die CMOS CPU was the RCA 8-bit CPD1802, introduced around 1974-75. I was able to overclock it (perhaps one of the first overclocks on the planet), from 3 MHz to a whopping 6 MHz (MegaHertz)! And yes, it still runs at 6 MHz. Consider that the IBM PC used NMOS-only technology (5MHz i8088) 6 years later, the CPD1802 was so "advanced," it hardly got warm even at 6 MHz. So why do we need heatsinks on our CPU these days??? It's because the faster we switch the CMOS devices, the more often tiny capacitors need to be charged and discharged. This is increased work, and work is heat. So as we increase CPU (switching) "clock" into the GigaHertz range, this capacitor charge/discharge becomes the dominant effect, and when you have literally billions of tiny capacitors and MOS devices on a die, both the transistors (they are not perfect, they do have a small amount of ON-resistance) and capacitors will heat up. Therefore, a modern CPU in the stopped state, or near-stopped state, can be cool, but when running at 4 or 5 GHz can produce the heat of a 100 Watt light bulb. Now you know why intelligent clock throttling is important for the sweet-spot-on-the-tennis-racquet, especially in a laptop: computing power (and heat) on demand, only when really needed. This was supposed to have been a short comment.

[@hiepchu6028]

So useful video

[@saewings4963]

How come this has a Korean subtitles? thank you for this quality content

[@andreamaral9725]

I think Moore's law will probably last a long time, something like dlss comes to mind, while the performance jumps for gpus have been relatively small for the most part (e.g 3060-4060), there will almost always be a smarter/better way to get more performance (e.g frame generation)

[@Tyuwhebsg]

good video, thanks 😊

[@alpha007org]

You should negotiate with TSMC to put this video on their website.

[@dumle29]

I'm curious where you found the "pmos is more effecient" claim. I've googled a fair bit, and have been unable to find any good sources that detail / explain it. Only some poorly translated websites or Ai generated blog posts that claim it with no explanation or references. Im curious what would make pmos more effecient than nmos, as hole mobility is a little under half of electron mobility, which would make pmos generally worse at power handling.

[@HighYield]

I think this is a good read on PMOS vs NMOS: www.wevolver.com/article/nmos-vs-pmos

[@dumle29]

@@HighYield yeah that's one of the ones I found. It seems weird. It at least has a few fundamental mistakes, like when describing the pmos. They write that it's on when vgs is 0v, and to turn it off you apply a positive voltage. That's for sure wrong, it's off when vgs is 0v, and conducts when. A negative vgs is applied. They're clearly describing it as a high side switch, referencing the voltage on the gate to some arbitrary ground in their circuit. Not vgs They do cite another article on the same page for this, and that page does get it right. They also don't mention the power effeciency, though I did see that in a different very similar article.

[@NN-gb5lf]

It's ultimately all about the carrier mobility, which is no longer a straightforward number for either holes or electrons in modern nodes (see: strain, phonon scattering, effective mass, interface effects, SiGe inclusion etc). I can tell you that in modern nodes, the mobilities (and final Idsat per Z) of the two are engineered to be roughly comparable. Calling out a too-specific difference between N and PMOS as in the video is no longer warranted and may cause confusion.

[@NN-gb5lf]

Note that this is the only iffy aspect I noticed in an otherwise very well-done video on mixed-row design.

[@ILoveTinfoilHats]

The easiest way to explain it is that an electron is easier to move than a lack of electrons ("holes") Imagine trying to move a card by blowing air vs sucking air. It's easier to push.

[@Shrek_Holmes]

at <a href="#" class="seekto" data-time="105">1:45</a> what you should have said is enhancement mode and depletion mode not n type and p type tbh.

[@HighYield]

NMOS and PMOS are more common and imho also easier to understand.

[@ElijahSamsonWiltonChen]

wow, youre brilliant. thanks

[@SmexiRedditorz]

I wish I have as good presentation skill as you. 😊

[@WEPayne]

Now we have channel is thin pipes thru and completely surrounded by gate. Called Gate-All-Around FET, or GAAFET. Where to next ??

[@privateerburrows]

You are confusing two orthogonal issues. P-type vs N-type is one thing. Depletion vs Enhancement is another. A MOS transistor that conducts more when the gate is energized is called an Enhancement type transistor. A transistor that conducts less when the gate is energized is called a Depletion type transistor. The four combinations exist: There are Enhancement N-channel and Enhancement P-channel, as well as Depletion N-channel and Depletion P-channel. The polarity and Enhancement vs Depletion are orthogonal things that you are confusing. Depletion type FETs (with doped channel that conducts unless a voltage in the gate acts to suppress its conduction) were more common initially, but are rare to find nowadays. They are certainly not used in logic circuits. So, I'm assuming you did not want to bring up the Enhancement vs Depletion dimension into this video, since the CMOS transistors used in logic ICs are always enhancement type, never depletion type. Assuming you simply wanted to explain PMOS vs NMOS, then the right way of explaining it would be to say that they are mirrors of each other, with NMOS conducting from drain to source when it has a positive voltage on the gate relative to the source, and PMOS conducting from source to drain when it has a negative voltage on the gate relative to source. You could also have explained why higher current is desirable: The higher the current, the faster the gates it feeds can be charged. Other than that, great video! Very interesting.

[@Tential1]

Wtf dude. At the end of your video you you basically did the transition to a brilliant ad and then there was a brilliant ad. Wtf was that lol. 😂😂😂. You were saying I hope you understand it and I was getting ready for the brilliant ad. This was very good though. I understood way more than I thought I would

[@possible-realities]

Traditionally, an NMOS transistor is able to supply 2-3 times as much current as a PMOS transistor of the same size (due to lower mobility of electron holes compared to electrons). As I understand it, this commonly leads to PMOS transistors being sized 1.5-3 times as big as NMOS transistors in standard cells. I was expecting a similar pattern here, maybe 3 PMOS fins and 2 NMOS fins, but all the examples you show have equal counts of both. Is mobility difference not relevant anymore due to velocity saturation, or are there other effects in play here?

[@picobyte]

Even in our modern micro chips the wave properties of electric currents are serious rf engineering magic. Charging and discharging even the tiniest capacitance at Ghz rates makes why our cpu's get so hot.

[@Jake-yt8ss]

man it boggles my mind every time when i think about how chips, in essence very very complex circuit boards are mass produced with sites and cells and transistors measured in nm.

[@UseFreeSpeech]

Wow, This is a really good Explantation. I believe Everyone could understand Your Video if the have any interest and the Topic

[@UseFreeSpeech]

*any interest in the Topic (Can’t edit This Comment Mobile)

[@SBF_FTX593]

I've invented technology which can take us to 1nm transistors but I'm trying to get in contact with someone at Intel but they are not answering my e-mails.

[@marcinkowalczyk647]

great video! any chance for a APPLE M4 die shots breakdown soon ?

[@roccellarocks]

Thanks!

[@krakadoros8605]

Congratulation for your presentation. I enjoyed it. Can you please explain with simplicity, like to talk in a children, what is exactly happens in a chip, for example a PLD, when more, than its suggested from its manufacturer, Volts flow through it ? Is it the heat that broke the tiny metal connections or something happen with the electrons, like disordering them ? Thanks in advance

[@m_sedziwoj]

<a href="#" class="seekto" data-time="885">14:45</a> this graph is misleading IMHO, because it show size of transistors, but what would happen when it would get to 0? Infinity? Transistors density is more what we should look. Because 10nm to 5nm is same jump in density as 2nm to 1nm (if they would represent real sizes). And we still have plan for next 10 years ready, and more in progress. But personally, I can't wait to see more optic compute, not quantum, but using light instead of electron. Because it would eliminate a lot power usage, and would allow to build real 3D processors, as our brain is measure in cubic not squares.

[@myne00]

The reason optic compute doesn't exist is because it's hard. It's also worth noting that these transistors are already smaller than the vast majority of light. For example, standard fibre-optic wavelengths are between 1200 and 1600nm. That is infra-red. Creating the deep ultraviolet light that produces these is an insanely convoluted process, so it is exceedingly unlikely cheap lasers in the DUV range to operate optical CPU's will exist any time soon. Of course, you can argue that DUV isn't required for optical processors, but even if you take 400nm bluray wavelengths then you're left with the reality of an equivalent processor being at least 100x larger physically. Optical in theory could be far more energy efficient, and stack easier, perhaps limiting its physical size to roughly the equivalent of a CPU + heatsink, but then you're still making something with the same precision of a modern CPU that's 100x larger. I can't see how that could be anything but 100x the price per equivalent unit. Yes, I suppose if you can 100x the effective hz it might make sense. 500ghz single cores would be interesting. I wouldn't be holding my breath for optical. Undoubtedly it will be used for things like PCIE and even USB, but processing isn't likely any time soon.

[@m_sedziwoj]

@@myne00 you missing the point, you don't take in to account frequency, and that you can use multiple wave length of light at once, which is already use in real chips. And ignoring 3D aspect, so more performance in less space. And I don't think we see it fast, 10years it is minimum for any bigger production. There are many challenges, but from all solution I know, this is only which could be step up from what we have today. Heat is problem, and transmission speed to, this is why we move to light for longer connection already, but this will be useful in chips to, but as I said, it still in research phase, or some elements are not have solution today.

[@myne00]

@@m_sedziwoj I addressed frequency and 3d. I'm not sure how you missed that.

[@m_sedziwoj]

@@myne00 And I addressed that is not 1 to 1 conversion. First, multiprocessing at base, because different wavelength can be use in same time. You don't even think about 3D at all, because you say "size" but, you have ^2 in mind, when going up 100x is maybe millimetre, and I did talk about cubs, so "chip" with size of 15mmx15mmx15mm, is not 15x bigger, is 15 000 times bigger. and optimization in path of "signal", we still waiting for 3d cache to be directly connected to cores not on side, latency is important. About size, don't forget that electrons and photos can be wave or particle depending on situation, so I would not bet that "transistor" must be of size of wavelength, because even today optic is not. And I not talking about optical processors, because they are more as 1st transistors, not even to compare to today one. Anyway, size in 3D change everything, even when size of "transistors" can't be smaller. As human brain is slow, each neuron is big, but still better what we have in chips.

[@myne00]

@@m_sedziwoj I clearly said the solution might be around the size of a cpu+hsf. That's 3d. You seem to be forgetting that a huge chunk of any processor is "wiring". Optical wires are thousands of times more sensitive to corners than electricity. So the "wires" are 100x bigger, and have bend radius limitations. As for your theory on dwdm in the processor, that's a whole other level of complexity.

[@cdgonepotatoes4219]

I love how the silicon wizards of the world are taking it personal when other engineers say Moore's law might be dead.

[@helmutzollner5496]

It was nit just interesting. It us enlightening. Thank you for ghe excellent explanations.

[@Walter_]

Omg mortal kombat deception text!!!

[@Winnetou17]

Interesting. I wonder if, using the same "dumber but with better materials" idea, we're going to see a move away from CMOS in specialized chips. I mean, we already have examples of 3 types of cores on the same chip for different performance and power usage levels. If you can use 1 normal transistor instead of 1 fat siameze transistor, then that should further improve the density. And only use these for more specialized chips, so the energy efficient transistors for energy efficient cores (or accelerators) and viceversa. And, surely, some chips will still need CMOS.

[@joechang8696]

I wonder if anyone tried multi-voltage gate? consider N-type depletion. 0V on source, 1V on drain. to shutoff the transistor, -1V is place on the gate. the (absolute) voltage differential between Gate and source is about 1V (0 & -1) but the differential between gate and drain is 2V (1 and -1). So partition the gate in 2 sections. the section closest to source could take say -1.1, put -0.3 on the gate section closest to drain?

[@azamatbezhan1653]

It would be interesting to listen about gaafet 14 angstrem that has 18 nm metal mitch

[@hupekyser]

drinking game: drink a shot every time you hear "so called" on serious note. i loved the so called 'deep dive' in to the so called 'transistor'. ok ok, ill stop. but i do genuinely love your work.