This is the BEST Board to Learn RISC-V Assembly.

[@gbulmer]

@Coding Neko asked a useful question. "Why learn RISC-V assembly [language]?" The video could say: 1. Learning assembly on any CPU helps understand what's _actually_ happening, and may help debugging. 2. Learning assembly for a RISC-V is rarely useful (except for point 3). C compilers for RISC ISAs mostly generate better code than an assembly programmer could write in comparable time. So C is much more productive. 3. Learning assembly for RISC-V might be valuable for writing: a bootloader, 'bare-metal' startup code (eg. code to replace program initialisation like 'C pre-pre-main') porting or implementing multi-tasking, or bootstrapping a programming language that isn't in C. There might be a few other cases eg: super-fast interrupt handlers, or porting performance-critical assembly from a different architecture. Some cases might be easier to write a C program with in-line assembly, but that still needs assembly knowledge. Problems where assembly might be essential involve resources C programs can't access (eg a CPU status register), or instructions the C compiler can't generate. However there are often 'C intrinsics' which generate those instructions, so needing assembly is rarer than it might seem. 4. Learning RISC-V ISA programming is better than learning a proprietary ISA because RISC-V _is_ open. Unlike other open ISAs, affordable hardware exists from multiple manufacturers, and RISC-V is increasingly being embedded in products. Summary: Understanding the underlying hardware helps us debug higher level languages eg C programs. The cases where assembly is _essential_ will likely become obvious quickly. 'C Intrinsics' might remove many needs for assembly language programming. Writing in-line assembly within a C program is often much easier than only raw assembly. Code space is rarely a problem compared to RAM, so don't worry unnecessarily about program size. With those facts, people have enough to reach rational. informed. decisions _(It took me under two minutes to read that out loud at my normal pace; so, not much extra.)_ It might be worth spending a minute or two on why the C compiler will likely do a better job generating code for a RISC architecture than most assembly programmers could do. I am not trying to dissuade anyone from learning RISC-V assembly language. I'm only trying clarify the reasons. Best Wishes All for 2022. (Sorry for repost, I spotted some mistakes.)

[@gbulmer]

@methosa8818 Thank you for replying. I believe your making a useful and subtle point: even though a compiler might occasionally generate an unusual instruction that does not mean the compiler has a good enough 'model' to fully leverage complex instructions. Further, the compiler writers might avoid them for generality. The compiler writers _might_ have avoided complex instructions like STMIA or LDMIA because, AFAIK, they are implemented as 'uninterruptible'. Hence those instructions might have a significant impact on interrupt response time. Worse, if the system has unpredictable interrupt latency it might be very difficult to track down. I have no doubt you can achieve significant performance improvements using STMIA and LDMIA. I've experimented with 'vector' instructions on PowerPC to get big gains. AFAIK, the RISC-V designers elected to keep system state simple, and avoid multi-cycle uninterruptible instructions, Hence I AssUMe (but have no actual evidence) there are few circumstances in end-user applications where hand-crafted RISC-V assembler would beat C compiler generated code. Of course, I might be wrong!😀 Thanks again for replying. Best Wishes. ☮

[@pascalcoole2725]

Now that is a real good tutorial ! No long bullshit talks just to increase viewtime... straigth to the point, enough to get going, the rest is just a mather of figure it out yourselve (if unable, you're unable to code any assembly anyhow)

[@ikefir]

A deeper dive into linker scripts will be awesome as well. As always great video! Archived.

[@LowLevelTV]

Great suggestion!

[@aakashhemadri]

Yes a deep dive would be nice, a more general view into why and how they work

[@ragd4L]

And bootloaders too

[@kayakMike1000]

Good idea.

[@albertmagician8613]

There is an insane expertise needed to use gcc linker scripts, while this should be totally superfluous for assembler.

[@rampage_sl]

I feel lucky to find this channel.

[@KenJackson_US]

The finished code is shown at 10:06. Don't you need something after calling the function *("jal puts")?* I would think jumping to halt *("j halt")* would be appropriate. As it is, it looks like you'll fall through and execute *puts()* again with no return address on the stack.

[@BruceHoult]

Kind of, but it turns out it's harmless. This code doesn't actually use the stack, or RAM at all. The jal puts the return address in the RA register, and ret jumps to whatever address is in RA. And nothing in puts changes RA, so it will actually execute puts in an infinite loop. A0 will still be pointing to the null, and so the printing and incrementing of A0 will be skipped. It's a 4 instruction infinite loop. (5 actually, as that li UART_BASE expands to an AUIPC and an ADDI)

[@JGHFunRun]

I apparently noticed this and moved halt so that it was right after _start. I also, far more consciously, forced _start to be at the start by creating a .text._start section. It doesn't matter for this project but if there are any other files it could be an issue, and since there are other unused sections I decided to add it

[@aliraheem6135]

I might be missing something but wouldn't it be better to explicitly jump to halt after returning from puts. Works fine here but it's cycling through puts_leave with a0 pointing to the null, but in a more complicated program you might run some code without intending to.

[@BruceHoult]

You're absolutely right. The ret jumps back to the instruction after the jal, which is the start of puts. It loads UART_BASE again, loads the null again, jumps to puts_leave, and the ret jumps to whatever is in RA which is still the address of puts. Forever, since a0 is not incremented. Another fun fact: this program does not use RAM at all, including the stack, so initialising SP was a waste of time :-)

[@aakashhemadri]

Amazing! Waiting for just this tut

[@hex8675]

What starter kit would you recommend these days? Sparkfun hasn't had them in a bit and they don't seem to have an estimate for when they will be back.

[@markmanning2921]

Wrote a nice risc-v assembler in forth and was going to write a risc-v forth compiler + metacompiler but work got in the way lol. Its not abandoned...

[@NootNooter]

At 11:25, I do not understand how you got to the address 0x20010000? Where is this mentioned? I searched for the manual pdf of the RED-V SiFive chip and it said in chapter 5 "Boot Process" a table, but it says a very different number? Edit: I was looking at G003 manual. In the G002 manual for the E310 it did say 0x20010000.

[@davidgrisez]

It has been a very long time since I have done anything in assembly language. Many years ago I had a Heathkit 89 Computer which had a Z80 processor. I did do some simple things in Intel 8080 assembly language.

[@jasonlhb]

Z80, i8080...I learned these 2 during senior high. I bet you probably was born in 60s, right?

[@davidgrisez]

@@jasonlhb I am older than that, I was born in 1951. The very first computer I did any programming on was an IBM 1620 at a junior college.

[@KenJackson_US]

Oh man! Those were the days, David.

[@OpenGL4ever]

@@KenJackson_US These were the times when it was easy to get rich by programming as the software projects to be programmed were much smaller than today. Nowadays it often takes a team of programmers and man-years to implement a larger successful project.

[@icryo]

Concise! Keep it up! Very High Quality!

[@LowLevelTV]

Thanks, will do!

[@aakashhemadri]

Could you perhaps look into trying out running riscv code on a Longan Nano a gd32v board. Is quite inexpensive and great for beginners!

[@doomsk888]

I would love to ser that as well. Struggled some time ago to make assembly code to work on it. This video gave me hope back to try again though

[@edgeeffect]

Thanks.... I'm looking for a less featured, lower priced board.... I'll havea look for a Longan.

[@turanamo]

+1

[@diegomasotti7517]

Wait wait... wait. Multithreaded programs in assembler? Is anyone that masochist to even try that?

[@LowLevelTV]

It’s very possible!

[@dlol.]

@U P i fear you keep it up!

[@Jair_inacio_Neto_Teixeira]

@U “Amali L” N can you name a book where I can find such a theme? I'm kind of masochist when it comes to low level haha

[@kayakMike1000]

yes it's hard, but running io stuff on a thread is great no matter c or assembly. It feels so good when you get it to work!

[@BruceHoult]

all programs, including multithreaded ones, are ultimately in assembly language. You can't implement a multithreading OS or library *without* hand written assembly language.

[@kevinclaypool6345]

I really really really appreciate that you did this video for the asm newbz to riscv, but if I'm being honest, I left feeling even more intimidated by the amount of code I was unfamiliar with...

[@embeddedbastler6406]

So QEMU automatically prints the data that is written to UART to stdout?

[@LowLevelTV]

Yup!

[@brunoparis10]

i don't see text after

[@BruceHoult]

If you specify "-machine sifive_e"

[@bennguyen1313]

I like the $8 ESP32-C3FH4 RGB board.. it has a Risc-V but also includes Wifi, Bluetooth5, couple buttons, 25 leds, etc. However, not sure how debugging works on it. For example, I understand gdbserver runs on the target cpu, and that the host cpu must interact with it using openocd/jtag... but what's the general approach on setting that up? I know Percepio sells a "Tracealyzer" that can save snapshots of your FreeRTOS project, for analysis. Perhaps the same is true with CodeWalker and Micrium uC/Probe? I'd like to see real-time live streaming of the data. BTW, any thoughts on the 'Timeless Debugging' talk given by the legendary George Hotz?

[@djsbriscoe]

Which board would you recommend TODAY? This particular board appears to be unavailable. Thanks.

[@reptilicusrex4748]

Excellent introduction. A deeper dive into this board/programming would be appreciated. Also as Trumpet Sock mentioned, a deeper dive into linker scripts would also be appreciated.

[@edgeeffect]

Yeah.... linker scripts are a "can of worms".... I've seen some tiny, simple linker scripts that just blow my mind in their sheer size. :)

[@ClearerThanMud]

I think learning SOME assembly language will teach you a lot about what's actually happening under the hood. And if you are trying to create very fast code, you can ask Compiler Explorer to show you the assembly code for your Rust or C code and see whether it is what you expect. OK, but that would be true for ANY assembly language, so why RISC-V? First, because RISC-V is about the easiest, most straightforward ISA you will find. You won't gain any extra insight into what the hardware does by learning a mess like the x86 ISA, and that would be a LOT more effort. And RISC-V is probably going to be a BIG DEAL in small embedded systems, so knowing it could help you in your career a few years out.

[@OpenGL4ever]

Maybe you won't gain any extra insight into what the hardware does by learning x86 ISA, x86 ISA uses microops anyway, but you will learn and understand what the compiler does and you don't have to buy extra hardware if you already have an x86 computer. There's nothing wrong in learning just both. And they both have a different target market anyway. You will very likely not program in x86 assembly for embedded systems. Today x86 is for performance-hungry or large software tasks with plenty of CPU power and memory. Risc-V has to serve this field first and when it does that, then you will have a very special workplace, because the majority use x86 for something like that anyway. So there is no x86 or RISC-V decision to be made, the two usually just don't get in each other's way at the moment.

[@mikafoxx2717]

@@OpenGL4ever yeah, basically if you're learning assembly, it should be ARM m0, or RISC-V, or maybe esp32 whatever else x86 would be silly unless you're in the habit of reverse engineering software

[@sparkybrit]

Nice! Why not define a .uart section in the linker script to make everything relocatable?

[@pj4x69]

Hey very nice tutorial 👍 Could you maybe make a tutorial how to use the gpio on the sparkfun red-v

[@chillbro2275]

Wow! So does the document saying how to link a program to the board come with the board?

[@JeffersonRodrigoo]

Great content and didatics!

[@ostanin_vadym]

Thanks for the content

[@stonered8760]

However the capacity of the on-board flash chip is 32 Megabits(Mb) instead of Megabytes(MB) according to the official schematic.

[@edgeeffect]

This is much easier than the complex fooling around I have to do on an STM-32.... it's like a return to the simplicity of the AVR.... maybe even simpler.... I certainly have to look into this chip.... it's not just the RISC-V, it's how easy they've chosen to structure the microcontroller's peripherals too. NOW if someone would just bring out a board without all that SPI flash, USB port and other things I don't need for Blue Pill prices.... now that would be delicious.

[@theVSORIGINALs]

how much should i know to do this i m taking a computer science degree and i m in last year i know only basic commands like ld,sw,jal, etc

[@chillbro2275]

Holy cow, i was already subscribed?!? haha

[@alurma]

Thank you very much!

[@rallokkcaz]

Low level gang!

[@str.haysam]

Hope you do a video how to setup rust to code for a RISC-V

[@johnasleyw]

Thank you

[@EdwinFairchild]

you didnt mention how much ram that puppy has?

[@minirop]

sparkfun's store says: 16 KB Instruction Cache, 16 KB Data Scratchpad

[@EdwinFairchild]

@@minirop thanks, i have not heard the term scratchpad before at least not in embedded.. interesting

[@cccmmm1234]

It is RAM that can be used as RAM or as data cache.

[@BruceHoult]

The funny thing is this program doesn't even touch the 16 KB of RAM once. Not even the stack he sets up. It'll go a long long way like that.

[@LiamDennehy]

It would be nice to see that difference between the compiled binary and the hex file.

[@cem_kaya]

does it have any type of cas or faa instructions for multi threaded data structures ?

[@BruceHoult]

The chip implements LR/SC and AMO{SWAP,ADD,AND,OR,XOR,MAX,MIN}

[@cem_kaya]

@@BruceHoult have to read about it thanks

[@kacperfilipek8461]

Looking at a thumbnail I thought the red board was MSP430

[@LowLevelTV]

It looks VERY similar.

[@abdosoliman]

would it kill hardware designers to agree on a similar memory structure, just imagine If there was an IEEE standard for Memory addresses for stack, heap, code, etc. it should be theoretically possible, at least for civilian commercially available hardware. wouldn't that be nice not having to go grab a spec sheet to write a linker file?

[@captainswing4040]

please make a detailed video on qemu emulation please please

[@olafbaeyens8955]

On the physical board I am somehow stuck. In your example you have msg in .rodata (that is read-only) and that works If I move msg in .data (that is read/writable) then a letter "C" is written and not the string, so somehow the message string is not there or I have a wrong pointer. I think I need a boot.s that is more extensive than setting up a stack and getting the Hardware thread 0. I assume that .rodata is running in flash memory and .data needs to get copied, but I can't find the way to do it so far by surfing on the internet. A more advanced boot.s example would be nice in this demonstration.

[@olafbaeyens8955]

I cracked it, on the board the linker file must be more extensive and you also need a boot.s that copies the .data from flash to SRAM and clear all bytes in .bss. I used chatGPT to help me in this. ChatGPT does causes some issues, don't trust the code it generates. The linker file is too big to post here and I don't have a working example to show off worthy to be shown :-) .rodata = constants that is red-only and only reside in FLASH .data = data that is initialized with data you copy from flash to SRAM once but free to be modified later on. .bss = data in SRAM that is just set to 0 just before you enter main.

[@olafbaeyens8955]

In the linker file you need something like this: MEMORY { FLASH (rx) : ORIGIN = 0x20010000, LENGTH = 16K RAM (rwx) : ORIGIN = 0x80000000, LENGTH = 16K }

[@olafbaeyens8955]

In the sections you need something like this: /* Code and read-only data goes into FLASH */ .text : { _stext = .; KEEP(*(.text)) KEEP(*(.text.*)) KEEP(*(.rodata)) KEEP(*(.rodata.*)) _etext = .; } > FLASH

[@olafbaeyens8955]

For data you need something like this: /* Read-write data goes into RAM */ .data : { _sdata = .; _data_flash = LOADADDR(.data); KEEP(*(.data)) KEEP(*(.data.*)) _edata = .; } > RAM AT> FLASH

[@olafbaeyens8955]

BSS: /* Uninitialized data goes into RAM */ .bss : { _sbss = .; KEEP(*(.bss)) KEEP(*(.bss.*)) KEEP(*(.noinit)) _ebss = .; } > RAM

[@echoptic775]

Why did you provide the _end symbolwhen you never used it?

[@ScreechingBagel]

3:18 four keys + enter pressed, it's probably "user"

[@tetraquark2402]

Still trying to get my raspberry pico to work with something more complicated than blink so I'll skip getting one for now

[@StevenJoseph-ob6ru]

Nice!

[@marcsmithsonian9773]

Can yiu code doom to see if it moves faster then on my 150mhx SGI indy

[@platin2148]

Suspect there are flags for clang to build too riscv?

[@BruceHoult]

Absolutely. LLVM/Clang promoted RISC-V from experimental to official in February 2019.

[@rohithvishaal]

Hey this is random video to text on but can anybody guide me on how to start understanding low level stuff. Let's say i want to reach a level where I can program an micro controller in assembly by looking at its documentation 😅

[@adsick_ua]

Nice vid, but I'm not so deep in low level asm stuff, I'm a Rust programmer. What would you recommend to watch/read to understand what is going 'ere? (I'm interested in RISC-V as an open architecture)

[@somberrhombus]

I keep wanting to buy one of these and a book on RISC-V assembly, but it feels like I should wait for something a little more powerful.

[@OpenGL4ever]

You can buy a book on RISC-V assembly and use QEMU RISC-V emulation on your PC until you found something more powerful. Don't wait for the hardware.

[@somberrhombus]

@@OpenGL4ever Its funny that in the time that has passed since my comment I've gotten a fairly powerful quad core RISC-V board.

[@OpenGL4ever]

@@somberrhombus Well then, nice to hear.

[@ElectronicFanArm]

Oh god clickbait or what!!! Today tons of ESP32 and RISC V recomendations why!!! xD If I want to use ARM Should I move to RISC-V?

[@afnDavid]

How many boards have you zapped with poor handling from ESD (static discourage)?

[@nacnud_]

Could have jumped to halt at the end.

[@parrotraiser6541]

A little bit of forethought before leaping into programming can save a lot of keystrokes and debugging time. A lot of that code looks like boilerplate that will be used repeatedy, in every program for the board. It should be set up beforehand, then included as a starting step, by whatever mechanism the local editor supports. The same is true of the compilation and linking steps. A lot of unchaninging operations, with only the program name changing. All that should be in a script.

[@BruceHoult]

I don't have the Sparkfun board but I have SiFIve's HiFive1 which uses the same chip. Their SDK has a start.s that does the boilerplate setup and the same for the linker script. I'd be surprised if Sparkfun doesn't give you the same stuff too, but it's still nice to see what the minimum actually needed is. He didn't quite make it as the check for HART ID 0 is not necessary on this single-CPU board.

[@esra_erimez]

This is all well and good, but how do you write a preemptive multitasking operation system for it in assembler? Subbed

[@KenJackson_US]

That's more involved.

[@olafbaeyens8955]

Why learn RISK-V? Or any other assembler language? 1. Because assembler is way more easy than any programming language. No OOP, No traits, no abstract syntax, no 1000 dependency packages, different frameworks.... Just you and your processor. 2. Force your brain to get out fo your comfort zone and become more creative. Even though you may never create big projects in assembler unless you are a virus writer. The knowledge can even help you create better high level code. 3. You are more focuses on your code you write. Every deploy is slow to debug so you must look at your code mere thoroughly and understand the code way better. Sloppy code will punish you big time, so quality code is enforced. 4. Learn to create efficient code, not bloated code like you used to have in any higher level programs. Your high level projects will improve.

[@rockpadstudios]

nice vid

[@cccmmm1234]

150 MHz early laptop? I wish... The first laptop I used was 10MHz or so.

[@BruceHoult]

Yup. My first laptop was a PowerBook 100, with a 16 MHz 68000 that took 4 clock cycles for the simplest instructions e.g. move one register to another, or add/sub/and/or/xor one 16 bit register to another. 32 bit operations took 8 cycles minimum. More complex instructions could take 12, 16, 20 cycles ... So, compared to this 150 MHz 150 MIPS 32 bit RISC-V chip, the M68000 was effectively 1 MHz (or 1 MIPS)

[@OpenGL4ever]

@@BruceHoult A 386DX 16 MHz had about 5,4 MIPS and an integrated MMU.

[@BruceHoult]

@@OpenGL4ever so did the 68030, but those are six or seven years after the 68000 and 8086, and much more complex chips. According to Intel's own 80386 Hardware Reference Manual "At 16 MHz, the 80386 is capable of executing at sustained rates of three to four million instructions per second". That sounds about right to me. But in any case, all these CPUs are at least 50 times slower than the FE310 on the microcontroller board shown in this video.

[@OpenGL4ever]

@@BruceHoult The 386 was released in 1985. The 68030 in 1987. The MIPS numbers for the 386DX are from the WP. 3 to 4 MIPS are the 16 MHz 386SX version or later 80386SL, not DX. The 33 MHz version delivers 11,4 MIPS and these numbers are quite correct, because the 486DX has more than double the speed at the same clock rate. (27 MIPS) Of course. Even my 16 year old Nokia N810 Internet Tablet with a OMAP2420 - 330 MHz ARM1136 processor that was released in October 2007 is faster than the old 386.

[@hand-eye4517]

can you make an update please sir ? there is a shortage of this type of content ! and there is a big updaTe to the hardware available

[@Killputin777]

what language is this? *.s file?

[@cccmmm1234]

Assembly

[@viktorstojanovic9007]

.s means its an assembler source file

[@Killputin777]

@@viktorstojanovic9007 thank you sir)

[@youtubeviewer7077]

taque is the french word for hyphen.

[@billshedd55]

They don’t make those anymore.

[@bobbastian760]

Red 5, Nigel Mansell

[@albertmagician8613]

Use larger characters. 24 by 80 is ideal.

[@abhinavlal3252]

Which linux distro are you using?

[@OpenGL4ever]

This doesn't matter. But i can highly recommend Debian stable for security and time saving reasons.

[@MuStevenPlay]

thank u i love u

[@jhoughjr1]

Not Five, V for Versatile!

[@AndrewHelgeCox]

New ESP32 devices are based on risc-v.

[@ogg3k594]

The blur on video is so horrible.

[@BrianG61UK]

You call (jal) your puts routine and then NOTHING! You just let it fall into the puts routine again!! Surely you want to halt or loop or something after calling puts?

[@BruceHoult]

he gets lucky with an infinite loop with t1 pointing at the null at the end of the string, jumping to the exit label since the byte is 0, which returns back to the start of puts again (since nothing ever changes ra after the jal).

[@233kosta]

Step 1: Implement a RISC-V CPU in FPGA Step 2: learn RISC-V asm Am I doing this right? 😂

[@mikafoxx2717]

You'd best be familiar with the ASM before designing the chip. :p But for real, the elegance of the base Isa is amazing for design. Set bits for register select, sign extension, and set shift offsets from instruction immediates to registers..

[@233kosta]

@@mikafoxx2717 Oh, I wouldn't be designing it, just lifting an FPGA implementation of an existing one.

[@DFX2KX]

that is not nearly as convoluted as I would have imagined.

[@espero_dev]

Hmm VMware or virtualbox but it looks more like VMware

[@TuxieBSOD]

"Same price" 42$ is not the same price xD

[@codingneko]

I don't...What's the point of this? Why would you code RISC-V Assembly instead of C? is there any actual advantage or is it literally just to flex?

[@LowLevelTV]

To learn! (It’s in the channel name)

[@penguin1714]

It's to learn how the hardware works... Love videos like this, but it'd be neat if he mentioned where he was getting some of this information from. Feels a lot an unironic version of the "how to code minecraft in java" meme because it looks like he's just typing code from another page without any reference as to where he got any of the information. It's still a neat video, though. Not shitting on it or anything

[@warlockd]

One of the neet features of the RSIC-V is since its so FPGA friendly, you can put in your own instructions. Usally they are DSP/vector custom packages that quire special libs but can do crazy things like multiply a grid of 32 floats in one cycle.

[@codingneko]

@@warlockd I didn't understand that but if there are actual reasons like what you seemingly mentioned to use this over a higher level programming language I'll stfu xd

[@rvgeerligs]

Look this stupid. Because it is reduced instructionset it is much more code to get to the same goal with cisc. What you want is a higher level language like c or even basic to generate the assembly for you.

[@godnyx117]

The best board to learn RISCV is QEMU.

[@kefsound]

Stop saying "boom".

[@JG-nm9zk]

ok boomer