TTL NAND gate with Totem Pole Output

[@indrakumar8414]

I can't believe after searching so many videos finally i got the perfect and accurate 100% explanation type of video... Thank you thank you so much for making this video... Your hard work paid off...

[@UNMEASURED100]

You are a savior.

[@sherlinjesudhas3624]

The best video for TTL in youtube!... Thankyou sir!!!

[@amitdeshwal2860]

Brother with your help i have attempted ttl three input nand gate in paper, Thanks alot bhai....☺☺

[@shubhamkothari2709]

Great. After hours of searching finally got the best one.

[@gokuvegeta9500]

Very well done! I loved this video. Play it at 0.75x speed

[@abdullah_al_zobayer1215]

Brother ,Thank you very much....This topic is in out syllabus....Thanks......

[@ashlyp7804]

Well explained.. Please reduce the speed

[@alenatraj5707]

aweome and very well explained that our teachers in colleges cannot not explain like this THANK U VERY MUCH

[@SahebjadePage]

ALE NATARAJ

[@lakavathgopi7541]

...... Excellent explanation.........

[@gayatribarhate5137]

very good explanation sir

[@tanjidhossain4348]

Thank you sir, you made it really easy to understand. proud of you. #iiucian

[@amitdeshwal2860]

i will score full marks tommorow in 3rd sem papers

[@ioanadobos2840]

This is really nice, thank you

[@parthgabani9942]

Great explanation!

[@parthmodi4181]

how q2 acts as phase splitter

[@akashmandal6335]

very well explained sir!

[@veedapusiddhartha4895]

Perfect lecture sir

[@shrutitripathi6347]

thanks sir...its very helpful for me..

[@amitdeshwal2860]

Bro you rock☺

[@pedromaju]

Why the current dont flows trought the base of Q3 when Q2 is ON?

[@raselrahman3822]

when Q4 is On ,its base is at .7 w.r.t ground .Q4 gets base drive from Q2 ,So when Q4 is On ,Q2 has to be On . Therefore Collector-Emitter volt Vce-2 is .3 (saturation value). Hence Vb3 =Vc2=.7+.3=1 v For Q3 to be On it's base-emitter junction must be forward biased. If Q4 and Q3 want to be conducted simultaneously ,D 1 needs to Active . so the base volt of Q3 must be Vb3= Vce(sat) + Vd1 + Vbe3 =.3+.7+.7=1.7 Since ,Vb3 only 1 V when ,Q4 is active . Hence , it can be said that Q3 And Q4 can't be conducted simultaneously .

[@wariskn7096]

@@raselrahman3822 u have mention vsat which transistor vsat are u talking about?

[@RixtronixLAB]

Cool :)

[@binodkarunanayake]

What is the importance of D1 diode?

[@Rocks740]

Totem pole configuration That's it

[@AnkitKumar-iu2rs]

Bro,this is amazing.Its really very helpful for me..but don't mind plz explain your concept in slow..don't be fast..

[@EEAcademy2022]

Ha ha....I actually talk fast...Could not help with that....

[@shinzon0]

the way you say "stage" is completely ununderstandable... have a look at the "-ge". Thanks for the video :) The same with "voltage", you say "voltace" and "stace"

[@gayatribarhate5137]

sir can you have a tutorial on How to design 4 bit parallel adder using IC 7483 and NAND gates only plz plz plz sir plz do a tutorial on this

[@gayatribarhate5137]

this a very imp ques may i can have it in my ques paper in semesters plz sir do a tutorial on this

[@SLRNT]

Maybe you should work for your degree instead of asking others to do it

[@shrutitripathi6347]

sir pls tell me which transistors is used in this circuit...

[@swapnilg.5996]

shruti tripathi common emmiter

[@ganeshvhatkar8853]

NPN Transistor

[@athiragopalakrishnan9359]

osm sir

[@vrushabh1816]

Bhest video sir

[@thelostarc9516]

good, keep it up.

[@anniechaudhary6007]

ACHA RE,.

[@dineshsaraswat40]

At 2.05 min, when base of Q 3 is zero Why is base of Q4 one

[@indrakumar8414]

It's bcoz if Q3 will be 0 then Q4 will be 1 ,reason is transistor Q2, which acts as switch... just remember at a time only one of the two transistor in tottem pole i.e Q3 and Q4 , only one can be high...

[@harishkumar-sp5ij]

Our teacher should learn how to teach the subject

[@saurabhmathur5149]

Cant understnd what you say😑

[@EEAcademy2022]

bad luck then...

[@randycordero4729]

you speak too fast