TTL Open Collector NAND Gate

[@ichwanwiradarma8518]

Bon, regarder j'esp'ere aussi de'j'a le partage....., ce tellement et qualite' au top. Enorme'ment de plaisir 'a avoir suivi, et je suis attende des videos 'a regarder.

[@IbrahimKhan-is2bg]

sir, the voltage at both forward biased diodes will be either 0.3 or 0.7 volts not 0 volts I think.

[@vinitgrover3570]

Is totem pole output same as active pull up ?? Plz reply

[@madhurireddykagitala3585]

Sir y ur saying we aren't achieving a proper logic 0/1 wen no pull up resistor is connected.. Justify

[@JoshMn]

sir when both input voltages are high , you've taken voltage drop across i3 as base emitter voltage of Q4 here. but in totem pole nand gate configuration you had used voltage divider rule to find voltage drop across i3. why?

[@JoshMn]

EE Academy yea sure sure sir. thank you

[@gayatribarhate5137]

very awsome explanation sir my teacher should teach from you ...i understood everything sir i have a humble request can u have a tutorial on how to design 5 bit parallel adder using IC 7483 and nand gates only plz plz sir u explain everything so clearly ...plz plz sir

[@keshavrai9817]

Sir i didn't understand why at logic 1 or 0 the diode is becoming an O.C. or C.S.

[@EEAcademy2022]

When a diode is forward biased ideally it acts like a short circuit and open circuit when it is reverse biased

[@keshavrai9817]

so basically if vol across anode > V across cathode : FB ...ryt?

[@EEAcademy2022]

yes

[@Rocks740]

What is the advantage of using open collector out out when compared to totem pole out out Let me know please 😴

[@Gurpreetsingh-ez9jp]

sir rather than explaining ckt operation you shd tell about our aim mean meaning of open collectr its need...wasted 14 minutes.

[@EEAcademy2022]

In the very first minute, I said I will show the operation of the circuit. It's not because of me, you wasted your 14 minutes because of your stupidity.

[@dm3248]

gurpreet singh idiot you can read it's uses on google.

[@mrohitsingha1615]

This guy is bengali