Tutorial 3: Verilog code of Half adder using Behavioral level of abstraction

[@joffinjoy555]

Sir there is two AND gates in RTL .we mentioned only one HOW we got that

[@knowledgeunlimited]

Ex-or gate implementation for sum also taken care. And one more thing in behavioral level of abstraction the optimized netlist will be synthesized by synthesizer on it's own.

[@matambasavaraju3430]

@@knowledgeunlimited we have not got carry in RTL

[@akallrounder6846]

Sir. Cant we write testbench on the code itself sir?

[@nextgmeet7833]

no bro, we have to write separately

[@zyggzag4154]

Thank-you!