Tutorial 4: Verilog code of Full adder using structural level of abstraction

[@ravitejakukudala1368]

great explanation

[@pavimahi4501]

Hi sir. How to write a code for self checking test bench for full adder.please upload any videos for this topics.

[@knowledgeunlimited]

Try by writing a task which will check the output with expected output.

[@madhavareddyketha6688]

How to link test bench to the main verilog code

[@knowledgeunlimited]

It will be linked automatically...since you use . operator to map pin's.

[@madhavareddyketha6688]

If I want to give the inputs externally, how it will be done ?..

[@knowledgeunlimited]

dump the code into FPGA board and verify.

[@parmarpraful5111]

I need your help sir, for TCL scripting language