Verilog practice questions for written test and interviews | #1 | VLSI POINT

This is the first video of verilog practice questions playlist. Here you will get verilog practice problems online. In this video you'll get verilog questions and answers. This verilog coding is specially for beginners, which is very helpful for written test. Here in this quick tutorial which is a verilog programming tutorial for beginners, students will get verilog hdl interview questions and examples. In this video you'll get 10 verilog practice questions with answers.These questions will help you revise all the verilog programming concepts for written test and interviews.
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Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar

[@MukeshKumar-vh6zp]

Thanks 🙏 mam For providing such a important questions with discuss

[@ZakirHussain12345]

@2:11 format specifier must be ℅s instead of ℅name

[@preetamdewangansirclasses2502]

kindly keep making these kind of questions....excellent videos and helpful also...thanky mam

[@bishalghoshb3412]

Thanks You. I think u r the first who r doing verilog code into the next level in you tube.

[@vlsipoint]

Thanks you so much Akash, keep watching ✌✌

[@mayankkaushik1091]

Best video which totally based upon the questions on Verilog Impressive 🎉

[@vlsipoint]

Thanks a lot!

[@AkbarRajaei]

I use VHDL, and beginner with Verilog. Very nice tutorial 👍🏻

[@vasantabingi6958]

It's really helpful madam, Thank you 😍

[@sindhujavelayutham5663]

Very great mam.thank you so much.keep uploading more videos like this in verilog interview questions

[@vlsipoint]

Thanks for watching Sindhuja, stay connected ✌

[@monimilky]

your videos are very useful madam! I am seraching for dv role i have 2 yrs experience it is very useful for me

[@vlsipoint]

Thanks for watching! Stay tuned ✌

[@tharunkumar6823]

Your efforts are really appreciated.....thanks mam.

[@vlsipoint]

Thanks for watching Tharun!

[@youtubegoogle4163]

mam, answer of Q7 should be 4..... i think because if fractional part is >= 0.5, it integer converts to integer+1

[@hitechconclave8659]

Yes i think 4 is correct

[@DhanushH-g6d]

It does not take three clock cycles for Z to get the value of din in simulation; the update happens within one clock cycle. (5th one)

[@vinayanpa126]

For 5th question, all the statements will be executed in a single clock cycle irrespective of whether they are blocking or non blocking. The difference between blocking and non-blocking assignments comes into play when you have multiple assignments within the same always block, but across different lines of code. In the case of blocking assignments, they are executed sequentially in the order they appear in the code. In contrast, non-blocking assignments are scheduled to be executed concurrently after all the other assignments have been evaluated.

[@rahulsriram7179]

GOOD ..

[@vlsipoint]

Thanks

[@jyotirmoychatterjee7421]

In the last question what will it be rounded up to 11ns and not truncated to 10ns ?

[@nikitagalar5638]

Thank you ma'am 😊

[@vlsipoint]

My pleasure Nikita, keep watching.

[@spandandas9432]

Very Nice Video mam, for the last question why 10.5 ns rounds off to 11ns and not 10ns ?

[@vlsipoint]

For >=0.5 increment by 1

[@deepaksaraibhagi9612]

Thank you mam...really loved it....

[@pawantrivedi5531]

Where to get such types of problem for practice

[@kbnanusha4641]

Thank you Mam...

[@vlsipoint]

My pleasure, thanks for watching!

[@RamakrishnaReddy-nv1dj]

I am unable to join vlsi point telegram group

[@vincit1587]

Mam Ur having good knowledge in vlsi right , Can i know which ru currently working in ?

[@ushodayaa1034]

correct ans.10

[@DhanushH-g6d]

In Verilog, %name is not a valid format specifier and is treated as literal text in $display. Use %s to display strings, e.g., $display("Name = %s", name[80:49]); extracts and prints ASCII characters.

[@ushodayaa1034]

correct ans.7 correct ans.9

[@rameshbishnoi4510]

Ma'am verilog language complete krwa do jldi

[@vlsipoint]

Sure Ramesh

[@Bishnu_Papon]

For DFT ?

[@pushpendranayak3235]

Nice video

[@vlsipoint]

Thanks

[@chagaletiganganjaneyachaga8976]

In 10th question..why we maltiplied 11× 2(why take 2 ).?

[@harryshen4806]

a full clock cycle contains 0 and 1, 11ns of 0 and 11ns of 1(as you can see Z value is flipping), combined to form a 22ns clock cycle. thus the period is 22ns.

[@gvenkatesh6671]

Hi Madam, do some more question in Verilog

[@vlsipoint]

Sure Venkatesh, it will be uploaded soon.

[@yashsingh289]

ma'am don't use vibration in video ..it is very irritating

[@PremKumar-jq3wg]

For 10th questions how you multiple 10.5*2, where this 2 came from, would you mind explain

[@zebra00024]

​@@dhavalpatel_98imo it's not 10.5*2, it's either 11*2 or 10 by 2, based on if simulator will round or truncate time for that delay. What if you had precision 0.1ns? Instead of 1ns, I wouldn't trust interviewer who is asking that question without running that code. My honest thinking answer should be , check LRM or run that code in a sandbox

[@AjaysivanS]

to print the name use %0s not %name first ques

[@ASPIRANT-hw1qe]

the problem is u dont clr peoples doubts in comment section,,,,u just likes the comment where people praise u

[@neeleshranjan7827]

please someone explain me the solution of qn. 5.

[@DhanushH-g6d]

$strobe($time -> is right not $strobe($rime is right

[@vlsipoint]

Kindly avoid small typing errors if it is understood

[@DhanushH-g6d]

@@vlsipoint I can understand mam but not everyone will understand it know mam that's why I mentioned mam.

[@goshkianjali4934]

Make more vedios mam ....

[@IITMIAN_ABHILASH]

Mam why 11 is multiplying by 2.

[@zebra00024]

Because 11 is only half period, period measures length of a full cycle 1-0-1

[@nyang8888]

$display("NAME = %name", ...) the compiler is reporting an error. Try %s

[@verif_engg_vlsi6754]

Q3. P value is unknown because default value of reg is X, and reg is a 4 state variable (0,1,x,z) More over $display execute only once unless it is inside loop. Plz correct me If I'm going wrong

[@VishalOP_99]

❤ 💙

[@apoorvasrivastava7045]

q6 one more error is that wire is not used for output, how can we assign without wire.

[@sharmaji5298]

for output "out", by default Verilog will make it wire unless declared otherwise.

[@anandkumar-bd2ru]

In question no.8 break is not used. All statements will execute

[@divyamsatle6673]

50Mhz

[@AkbarRajaei]

The Telegram link has expired. Please share the new one.

[@jetoptimusprime]

These questions are too simple. Real verilog interviews will be based on company specific modules and are upwards of 75+ lines of code (for anyone that cares)

[@nilrathod9840]

Have you any channel for intermediate questions?

[@pushpendranayak3235]

Nice ...any new videos for interview point of view