How to create a Concurrent Statement in VHDL

Learn what concurrent statements are in VHDL, and how they compare to processes using sensitivity lists and Wait statements.
Concurrent statements are signal assignments within the architecture, but outside of a process.
When you create a signal assignment, you are implicitly creating a kind of process. Therefore, concurrent statements are sometimes referred to as "concurrent processes". By definition, a concurrent signal assignment is equivalent to a regular process with the same signal assignment and a Wait On statement at the end of it.
For example, the concurrent statement:
signal1 ＜= signal2;
is equivalent to this process using a Wait On statement:
process is
begin
signal1 ＜= signal2;
wait on signal2;
end process;
which is equivalent to this process using a sensitivity list:
process(signal2) is
begin
signal1 ＜= signal2;
end process;
There are more options to concurrent statements than what is presented in this video, but that's advanced VHDL stuff, so we will ignore that for now.

[@PL-VA]

Best explanation/coverage of this basic but important feature.

[@venkatm5443]

Well explained!

[@harykishore1914]

Please, zoom the screen so that it will be easy observe, now its so difficult to read those.

[@VHDLwhiz]

Sorry about that. Try to change the resolution to 1080p in the KZbin settings and make it full screen.