Virtual Memory: 12 Multi-level Page Tables

[@freyaj4666]

This series is awesome! I don't know how to survive college without all those youtube professors!

[@TheWischmopps]

this is so true!

[@raghavsrinivas9455]

These links has more clear explanation. It si not about swapping of tables. Above video seems missing important details .Watch these : kzbin.info/www/bejne/ppS3cqKvr7xlqLs and kzbin.info/www/bejne/qoGafYyYe9eeZ5I.

[@Alessandro_Furci]

David i spent over 3 hours (!!!!!) trying to understand Multi-level Page Tables searching on the Internet. Now i find your video. THANK YOU VERY MUCH MAN. Perfect lesson.

[@smitjainsj]

This is a million dollar video series about Memory Management.. big thanks to the creator

[@biogirl18]

Oh, My. The best teacher I have even seen. Willing to pay for your full knowledge.

[@罗林-k5n]

I am a software engineer , this series helps a lot, thank you youtube professor

[@omkars764]

These videos are awesome. Thanks for explaining them so well.

[@IK-ow2zk]

Thanks a lot for this course! You made an amazing visualization! It is brilliantly clear, and so recognizable!

[@MichalMonday]

It's great that it's clearly explained why it's needed (at 01:30). Previously I checked 3 different resources (course, book, website) and couldn't figure it out

[@pythonprofreak7522]

I like all your instruction videos and they are good for new and refresher learners. You have done exceptionally good job! Thank you!

[@catalinasdfghjkl]

the best explanation on the internet

[@ddnhan]

Thank you so much for making this video :D It helps me a lot to fully understand after reading the text book!

[@nilspin]

Question at 3:55 . Why 4kb + 4kb? In the video professor says "in order to do any meaningful computation" by which he means in order to perform any virtual-to-physical address translation we need atleast one 2nd level page in memory. My question is - but why? If an entry in 1st level page (in my TLB) says it's corresponding page is in Disk, can't I just fetch it from there like all other pages on disk that will follow?

[@lfm3585]

Rephrasing this question: Is it possible for a program to be running and have none of its data in memory. I think this depends on what you mean by running. If the program isn't in memory then you couldn't be executing any of its instructions. I think you are right that the application can be completely paged out and considered running by the OS

[@parasvaish3239]

Sure we can fetch the 2nd level of page table from the disk but 1. It still needs to be stored somewhere i.e. in RAM(since cache is small) so better keep a dedicated space in RAM from the start itself as fetching 2nd level table from disk every time will take up huge amount of time and eat up your performance. We can replace already present 2nd level table in RAM with another one as per our requirements.

[@gumsumful]

I simply wanna say you rocked =D

[@unknownxyz7885]

Thank you for clearing the concept of multi level page tables.

[@MrDajiangyoude]

This is truly illustrative!!! period.

[@klausdupont6335]

Incredibly well explained!

[@kr7437a]

i love it: "All problems in computer science can be solved by another level of indirection."

[@thelonearchitect]

Holy ! Thanks you so much for explaining so clearly !

[@onwul]

Great video, thank you so much!

[@960peps]

These videos are fantastic. Thanks !!

[@cammiller7686]

thorough and concise. thanks

[@raytruong5882]

Why can't all professors be like him

[@silas3463]

Hey David, really enjoying these informative videos :) I have a question about this video, when you ask "what the smallest amount of page table data should be kept in memory for a 32-bit application" you say that we need a 1st and 2nd level page table ( 3:44 )but wouldn't we only need a 4kB page table ENTRY for each page table?

[@abir95571]

You wouldn't want your program to start doing page swapping from the very beginning ... for the program to meaningfully translate some address it needs the first level page table and then any one of the 2nd level page table. Otherwise the program basically never "starts"

[@aldoramirezmendoza2663]

@@abir95571 But, If you don't use the program for a long time, the O.S could swap all 2nd level tables to disk, and that's not bad. So, you only have the first level table, that is only 4kB.

[@m.preacher2829]

without 2nd level page table u cannot index the correct PA in memory. so at least one 2nd level page table in memory.

[@tomaspinto3833]

Very good, but i still don't understand why we need 4kb+4kb instead of just 4kb. With just one table in memory, each entry is pointing to 2**10 (correct me if this number is wrong) different Virtual Page Numbers associated to their corresponding Frame Page Numbers. Why are you saying you need a second 4kiB table for translations if the translations are already there?

[@nilspin]

I was confused about same. Why 4kb + 4kb? In the video professor says "in order to do any meaningful computation" by which he means in order to perform any virtual-to-physical address translation we need atleast *one* 2nd level page in memory (at around 3:55). My question is - but why? If an entry in 1st level page (in my TLB) says it's corresponding page is in Disk, can't I just fetch it from there like all other pages on disk that will follow?

[@rubiskelter]

Seems like you've read the OSTEP?

[@eleftherioskostakis1834]

love you from Greece bro.

[@jonathanharris2326]

This is so helpful, thank you so much

[@Acadflix]

This is good, Priceless content. Multilevel paging is good in best case (meaning when each program access pages in sequence) but in worst case when program access pages each having entry in difference page table then i think IO cost will be too high because you will have to bring 2nd level page table every time you try to access a page frame.

[@warriorfb2010]

Very nice video. Great instruction

[@vi3ruSak]

So, even when you are using two level page tables, it can still happen for single process that it must keep one 1st level PT and all 2nd level PTs in memory in the worst case ?

[@hulaalol]

awesome explanation! thank you

[@chilo7272]

amazing work. Wish we could pring out that presentation

[@pp8471]

Very good material. Thank you

[@MyVip3r]

5:54 How to find which level of page table we need from the rest of 0x00402 ?how you devide these bits ?

[@fonera5131]

Throw 0x00402 into any hex to bin converter, split the binary result in the middle and you will get what he has there.

[@jonathanma4206]

Is it possible for the first 10 bits to point to a page in the 1st level page table, and the second 10 bits not found in the 2nd level page table?

[@johnc7331]

No because each level has a valid bit describing whether or not there is a page being used in that Page Directory Entry's page. For example, if a you have a 2 level page table, the top level will only be valid if in all the pages that it references, there is at least 1 page that references some address in memory. I hope I was clear in my explanation, if not just comment and I'll try and clarify!

[@taoyang5123]

Good video，just like OSTEP.Simple and best.

[@panzerofthelake1623]

So basically multi level page tables are basically page tables where each page table entry connects to another page table?

[@deepeshguragain2658]

Simply the Best........:-)

[@andychang1179]

This guy is amazing

[@flintthuang]

Is this multi-level page table a nested page table(EPT)?

[@abhishekknegi007]

Awsome explanation keep it up

[@tothespace2122]

At 1:54 what does 4kB = 1024 PTEs mean? We have 1024 PTEs because we divided our adress bits like this: 10 for first level, 10 for second level and 12 for bits taht are directly mapped. So what does 4kB mean in the context of first level table?

[@minhandrew3305]

Each PTE requires 4 bytes (on this 32-bit system we are talking about), so 1024 PTEs x 4 bytes = 4096 bytes = 4 kB in total for this page table in a multi-level page table.

[@cyberonymous4100]

Size of a page

[@aaditya4125]

the question @3:44, if we can have page table of less size, can we have the 1st level page table of 4kB and the 2nd level page table of 1kB each (since we will be left with 20 bits, so 2*10 bits, i.e. two 1kB page table) OR a 2kB page table ?

[@석상주]

Do we need 2nd level page table for every entry in the first level page table?

[@songlinyang9248]

Just the entries which the program need. Instead of all page table entries, we just need what we need.

[@thesquake5368]

@@songlinyang9248 So the ones that we don't need don't exist or are just simply kept on the disk ?

[@konakallaankalarao776]

Awesome explanation

[@w0nnafight]

nobody asked your opinion

[@jyotirmayaojha6516]

how do we know that a particular entry gives the physical address or is just another redirection to other page tables?

[@M_Dragon]

thank you so much!

[@wolfcompany2]

5:16 How does 0000 0000 01 = 3 ? Because 0000 0000 01 is technically 0000 0000 0100 = 4 ? So shouldnt this be pointing to 0x0004 instead?

[@parasvaish3239]

ig we are not matching tags over here instead we are using the value 0000 0000 01 as an offset from 1st memory location

[@ppugalia9000]

Wow.. this paging mechanism is cool

[@dharmikmistry8781]

awesome. thank you so much sir

[@przemek4101]

Will you make a video about EPT in Intel CPUs (SLAT in other words).

[@primitzisgate7]

what if we have N level page tables with TLB.Does it mean that first we look on TLB for the translation and if that fails then we go from 1 -> N level to find Physical Address ??

[@munipallynaveenkumar9866]

Thank you Very Much

[@jenweatherwax7113]

Life saver!

[@inordirectional]

Something I don't completely understand is how page table entries can point to disk in a fine-grained enough way. That is, what is actually in a page-table entry that is a reference to disk memory? Since page table entries are typically not that many bits long, they can't address the whole disk, which could be 1000GB, can they?

[@raghavsrinivas9455]

kzbin.info/www/bejne/qoGafYyYe9eeZ5I

[@abhinavaman8008]

I think we have page tables for each process. so number of entries in a page table is equal to the number of pages a process have not the number of pages secondary memory have. so 4MB would be the size if we have a page table for the entire secondary memory.

[@abhijeetchauhan4111]

In last question, what is the size for each application?

[@MyHarindu]

if the logical address is 64 bits and the physical address is 32 bits . how do i calculate the no. of entries in the page table? (page size -4KB)no. of pagea doesnt match with the no. of frames right? so does some entries in the page table doesn't has ita corresponding frame no?? am i doing this wrong?

[@iceszyeunicabautista3715]

what is a page table? is it a RAM?

[@OpenGL4ever]

Yes, a page table is stored in RAM. But a TLB is SRAM on the CPU die.

[@jstm]

Hi David, I want to clarify that this saves space method saves space by paging out unneeded page table to the disk, correct? For example if program A is running, then pauses, then its page table will be saved to the Disk, and when program A returns, its page table will be saved back to RAM? Also wondering why you would need 800 kb to store the 100 applications data, why wouldn't it be 1 * 4kb for the 1st level page table, and 100 * 4kb for the 2nd level page tables? Thanks

[@OpenGL4ever]

He says at 4:05 that you need 4 KiB + 4 Kib of memory for each application. This means one application needs at least 8 KiB. Then 100 applications will need 800 KiB.

[@poisonza]

appreciate the tutorials.. though multi level page tables need more explanation say.. single page table need 2^20 pages(page entries) ... 12 bit for offset 2 layered page tables need 2^10 pages(page entries) ? ... same 12 bit for offset since first 10 bits are used to access the second page table and second table only has 10 bits to represent the pages which is only 2^10? one of the way to make sense of this is to view 1st page table as chapters... 2^10 chapters * 2^10 pages but i am not sure whether this is the right way to think.

[@aviadshiber6232]

why each level need 10 bits? is that because we have total VPN of 20 bits and we divide it by 2 ? is it possible if the levels will not divide equally?

[@SamMingolelli]

8 bits are the page table's address, and 2 are the offset within the page table. You have 2 page tables so each uses 8+2 bits = 20 bits.

[@TomerS2210]

נו מה אחי גודל דף זה ארבע קייבייט וגודל כתובת 32 ביטים זה 4 בתים. אז 4 קייבייט חלקי 4 בתים זה 1024 ביטים גודל כניסה. אז צריך 10 ביטים.

[@difegui]

Hello! Thank you for this videos. I have a doubt: what would happen if instead of the address 0x004002204 would be 0x004003204? What happen when we find DISK in 2nd level table? I understood that all DISK parts were in 1st level in DISK Thank you!

[@SrajanBhatnagar]

+diego acetino I have the same doubt how was this number converted to bits ?

[@OpenGL4ever]

@@SrajanBhatnagar The number is in Hexadecimal. But difegui has one digit too many. A 32 bit hexadecimal number has only 8 digits.

[@akshaygujare1148]

Thank you

[@mohamed_khoudjatelli9349]

thank you :)

[@benmarcus2577]

why does each program need it's own page table??

[@Lisa-kk6go]

Each program has its own 32-bit virtual memory so it needs its own page table for the mapping.

[@dudas6699]

Holy shit, thank you for savin my ass. I finally understand

[@pisanghangus2]

thanks

[@deshanmithila6558]

hi,can u plz explain how to translate 00402 to 0000 0000 01

[@OpenGL4ever]

It's a hexadecimal number. 00402000 is 0b0000 0000 0100 0000 0010 0000 0000 0000 Bit 0 to 11 is our offset = 0000 0000 0000 Bit 12 to 21 is our 2nd level table = 00 0000 0010 Bit 22 to 31 is our 1st level table = 0000 0000 01

[@accio_biryani]

You can be a great GATE tutor in India, we are short of them

[@nicolastabet]

Legend

[@songlinyang9248]

Awesome

[@draganostojic6297]

TLB miss and PT fault

[@LnX53]

why cant i like this video fack youtube :(

[@randomTVSWE]

And the entries that dont go to a page table is directly mapped to physical memory?

[@marinacuello7598]

thank you so much!

[@LightMinz]

Thank you

[@taeukim1372]

thanks

[@w0nnafight]

your welcome