⨘ } VLSI } 26 } CDC, Reconvergence } LEPROFESSEUR }

[@ariklapid7]

5:48 Thanks for the video! Something doesn’t make sense here; We close timing between the metaflops and the capture FF. There shouldn’t be any glitch there. What can happen is a phenomenon called synchronization ambiguity. Propagation delay towards the D of the metaflop may vary between the two, so that one net is synchronized in delay. It is not a glitch issue. Meaning, we don’t know when the Q of the launch FF will arrive at the D input of each synchronizer; It may be launched and arrived an epsilon before SETUP (then it will take 1 cycle to synchronize), an epsilon after HOLD (then it will take 3 cycles to synchronize) or it may stabilize sometime before the posedge of the sampling clock, and then it will take the most common, 2 cycle-synchronization. But, even if both metaflops synchronize the signal within 2 cycles, nobody promises both will start synchronizing at the same time, because these are async paths

[@Leprofesseur]

thanks for detailed comments, typically in cdc paths timing is not closed by primetime or similar static timing analysis tools, it is considered false paths. Logic designers need to ensure correct mechanism for CDC. CDC tools (mentor's 0-in, now Siemens) are used to do CDC analysis and help to find out where in full chip CDC paths are, tools can dump out assertions which are then simulated to ensure that data los can be captured and addressed before design can be signed off. Microarchitecture and logic design need to ensure correctness that design. Every chip has standard procedures to handle on-chip clock and reset domain crossings. I hope this clarifies.

[@sharonbeaulah9210]

I have a doubt. Let's say two signals are coming from two different clock domains to a single destination clock to be used in a combinational logic. How to solve the convergence in that case?

[@Leprofesseur]

you may need to have some logic in Tx domain, e.g. combine both signals in Tx, flop resultant signal in Tx domain and then pass to Rx domain, synchronize it and use in Rx domain.

[@tvscharankruthik7661]

Video is interesting and helpful. I have a doubt. in the end, how are we solving the glitch issue? Is the solution, shown in the end a complete solution to CDC reconvergence? The glitch causes wrong value to be sampled by the 2- FF sync. right? Please clarify

[@Leprofesseur]

first sync flop latches the async value, waits for whole cycle before it passes the value to 2nd sync flop, in theory it should be good enough for 2 stage flops but sometimes 3 stages are also used, depends on various technology factors and clock frequency. These are specially designed flops to deal with metastability. however in designs other qualifier signals are typically used which act as enables with few cycle delays with some handshake/ack mechanism between sender and receiver, designers need to think about both data loss of signal in receiver domain and accuracy of signal. it is good idea to have handshake mechanism when clocks are not source synchronous. In high speed designs typically clocks frequencies and ratios are known and often source synchronous, there open loop cdc solution is also good, however designer need to make sure to have enough pulse width of sampled in receive domain to be properly sampled synchronously in receive clock domain.

[@sekaransekaran9487]

Thanks for the great information Could you please share details why Async reset de-assertion should be synchronised with clock

[@Leprofesseur]

if asynchronous, it will lead to unstable state in flops. It is required to have all flops in known state after de-assertion of reset.

[@gyaneshjha5167]

I think there still.lies the problem of reconnvergence glitch at the end we are using a combinational logic on the signal crossing the clock domain which is not correct we must always sync the signal first before using it. The ideal solution would have been to push the entire combo logic in the dest domain use a synchr. first then use combo logic afterwards. Am i missing something here

[@Leprofesseur]

my understanding is that push the combo logic in Tx domain, pass one wire to destination Rx domain, sync it before using via appropriate synchronizers from library. if you have multiple signals then it becomes more complex. Manny a times a global synch mechanism is used in combinations with local mechanisms of dealing with this situations.