⨘ } VLSI } 9 } Clock Domain Crossing (CDC) } FIFO } LE PROF }

This lecture extends the discussion on clock domain crossings. In this lecture design techniques for multi-bit clock crossings have been discussed. One can classify CDC signals in two groups broadly: control signals and data signals. For single bit control signals double flop synchronizing circuits or special library sync cells can be used safely. This becomes tricky if there are many signals (e.g. data bus) crossing the clocks. Two popular methods - FIFO (asynchronous FIFO, 2-deep FIFO), and MCP (multi-cycle paths) implementation techniques are heavily used in industry for CDC signals. This lecture discusses both techniques with a simple example.
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[@ravikumartiwari332]

Thanks a lot sir for your valuable guidance.... I ll appreciate and b delighted if I get lectures on some more topics like this...(related to FPGA for ASIC development like: How to implement clock gating, pipeline in our design and related issues, using vivado and 7 series FPGAs) in future.

[@Leprofesseur]

Thanks! for the positive feedback. I will plan some lectures on the topics you have requested in near future.

[@vazgengyoletsyan3933]

Hi Leprofesseur, thank you for the really informative lecture, Could you please explain , is there any approach of automatically detect Async Fifo in scope of CDC ?

[@Leprofesseur]

I am not sure whether I got your question properly, however my impression is that modern CDC tools in their reports provide detailed information that can be scripted to know various information related to clock domain crossings in the full chip design.

[@veer110]

Hi Leprofesseur, thanks for wonderful explanation. I had a doubt in fifo design, how write pointer and read pointer is made 1 bit ?

[@Leprofesseur]

Thanks!, it was not made 1-bit, it depends on how deep is memory, in the example it is 2-deep fifo so 1 bit is good enough, in general binary pointer values will need to be converted to grey code so that only one bit changes at a time across the clock domains.

[@mrshaaban]

Hello Sir, Thanks a lot for the valuable lectures. I have some doubts about the Closed loop MCP solution. Why do we need an XOR flop to generate a pulse, why couldn't we use an edge detect circuit? What if the EN signal is Hi for more than 2-cycles? Then the output of the XOR flop structure will toggle? Also, on the receiving side, why do we need an additional XOR flop if the received enable is already a pulse? Thanks,

[@Leprofesseur]

There can be many different possible MCP solution for CDC. In the lecture one example is discussed to give concepts. Typically EN signal is generated with intention in mind that it acts as one of the handshake signal. If EN toggle, one needs to make sure that it stays high enough to be properly captured. Idea for XOR along with flop is to generate a clock wide pulse for handshake mechanism. In theory you may not need extra pulsing if receive EN is pulse, however in real circuit, since signal crosses the domain, one can not be sure that signal will toggle with minimum one receive clock width due to delays associated with path depending of which technology library is used, so its good idea is to generate pulse in each clock domain to properly implement handshake mechanism. However, in real circuits FIFOs are typically implemented instead of example circuit described. All the best! LeProf }

[@mrshaaban]

Thanks a lot! It's clear now!

[@Leprofesseur]

you are very welcome! LeProf }

[@ashokreddy6552]

Thanks for the explanation on the clock domain crossing. I had two questions.. 1. When the data is crossing from slower(Source Clock) clock to faster clock(destination clock) which technique can be used? 2. When the data is crossing from faster(Source Clock) clock to slower clock(destination clock) which technique can be used?

[@Leprofesseur]

Thanks for feedback. Answers: 1. When signal is crossing from faster clock domain (source) to slower clock domain (destination), one needs to be very careful, implementation must fulfill minimum pulse width requirements in slower clock. One may implement open loop state machine based solution in faster clock domain or some mechanism which makes sure to fulfill minimum pulse width requirement. Another better way is to implement a closed loop solution with some sort of acknowledgement from destination back to source clock domain that signal value has been correctly captured and the signal can carry new value. The state machine or some logic in faster clock domain needs to make sure that data pulse has been stretched enough that there will be no data loss in slower receiving domain. 2. In case of signal crossing from slower clock (source) to faster clock (destination), its a bit easier. Nevertheless it must fulfill minimum pulse width requirements in the receiving faster clock domain. If source clock is minimum 1.5x slower than destination clock, it is safe, one does not need special logic in source domain. In both cases crossing signal must pass through a sync flop mechanism (double flop of special sync cell from technology library). Further, one may develop assertions to verify CDC protocol for pulse width checks. Best! Leprofesseur }

[@ashokreddy6552]

Leprofesseur } Thanks for your valuable explanation.

[@siddhipandya7510]

How to code this 2 deep fifo in verilog?

[@monikavijay2614]

can't we directly use multiplexer having EN as selection line instead of this XOR technique?

[@Leprofesseur]

xor could be modelled using multiplexers.