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VLSI | Fixes in Physical Design | Max/Min Delay | Max tran/cap | Crosstalk | IR drop | EM | Antenna

  Рет қаралды 25,250

Mahendra Maram World

Mahendra Maram World

Күн бұрын

Пікірлер: 53
@vikramadithya9597
@vikramadithya9597 Жыл бұрын
Nice video and well made. Thank you. Best video for last min interviews to cover the topics.
@mmkr
@mmkr Жыл бұрын
Thank you Vikram. Hope you found it useful.
@swathianumala2603
@swathianumala2603 17 күн бұрын
great lecture
@ashokanbalan
@ashokanbalan 3 жыл бұрын
Excellent video Mahendra. Keep up the good work.
@mmkr
@mmkr 3 жыл бұрын
Thanks for watching Ashok. Glad to hear that.
@RohitVerma-qu6eu
@RohitVerma-qu6eu 3 жыл бұрын
You explained extremely well. Actually, I keen to know the solutions more as compared to problem and you did the same. Thanks a lot.
@mmkr
@mmkr 3 жыл бұрын
Glad it was helpful. You’re welcome.
@alamurisanjeev5126
@alamurisanjeev5126 3 жыл бұрын
@@mmkr can you please do video on congestion issue and fixes in placement and CTS
@kodidalamaheshbabu9242
@kodidalamaheshbabu9242 2 жыл бұрын
Great content !! Thank you sir !!
@mmkr
@mmkr Жыл бұрын
My pleasure! Hope you found it useful.
@chintu8700
@chintu8700 2 жыл бұрын
excellent video sir
@mmkr
@mmkr Жыл бұрын
Glad to hear that. Thank you.
@DSPY1009
@DSPY1009 3 жыл бұрын
Awesome video. Keep it up and continue awesome work
@mmkr
@mmkr 3 жыл бұрын
Thank you
@KrishnaVamsikriative
@KrishnaVamsikriative 3 жыл бұрын
Great work👍.
@mmkr
@mmkr 3 жыл бұрын
Thank you
@chigururakesh9666
@chigururakesh9666 3 жыл бұрын
Ur explanation is simply superb sir. Easy to understand. Please do videos on Delay models like NLDM , CCS and AOCV, POCV/LVF.
@mmkr
@mmkr 3 жыл бұрын
Glad to hear that Rakesh. Thank you. For POCV, please check out my other video using the link below. kzbin.info/www/bejne/nXnRmWeenJ2emrM
@chigururakesh9666
@chigururakesh9666 3 жыл бұрын
Sure sir 👍
@mmkr
@mmkr 3 жыл бұрын
Thanks
@alamurisanjeev5126
@alamurisanjeev5126 3 жыл бұрын
@@mmkr Do you have any website
@trailblazerempire1293
@trailblazerempire1293 3 жыл бұрын
Indeed, Its an awesome video with good explanation. However, i have a simple question. You have not added, fanout violation here and yes i do see you did that split fan-out suggestion. In fact, we know once the transistion is fixed most probably we might not see fanout violation. However, I would love to know what are the given value for a max fanout and does this goes by process? Appreciate your kind reply.
@mmkr
@mmkr 2 жыл бұрын
Glad I could help. Thanks for watching. Please check the email for the answer.
@srikanta473
@srikanta473 3 жыл бұрын
Wonderful learning
@mmkr
@mmkr 3 жыл бұрын
Glad to hear that
@maheshreddy6217
@maheshreddy6217 3 жыл бұрын
Great Explanation!!! Can you please make a video on different types of files used in the physical design, what info do those files contain in them as well. example : SPEF, CTS SPEC, .tf, .lib, ndm, tluplus, .v etc. Also make a video on understanding various reports as well. Thank You!
@mmkr
@mmkr 3 жыл бұрын
Thanks for watching. I think there are some videos available on YT already on file types. But, I’ll think about making one on reports interpretation later.
@pavankalyan_varudu1515
@pavankalyan_varudu1515 3 жыл бұрын
Thankyou so much ❤️
@mmkr
@mmkr 3 жыл бұрын
You’re welcome. Hope you find it useful.
@shanwaznashipudi3895
@shanwaznashipudi3895 4 жыл бұрын
Great video. Can you please provide commands for sanity checks?
@mmkr
@mmkr 4 жыл бұрын
Thank you. Can you please e-mail (8mahe8@gmail.com) me if you’re looking for a specific information. Thanks.
@shanwaznashipudi3895
@shanwaznashipudi3895 4 жыл бұрын
Sure I will mail thanks for your response 🙏
@mmkr
@mmkr 4 жыл бұрын
Ok. Thanks.
@shanwaznashipudi3895
@shanwaznashipudi3895 4 жыл бұрын
Hi sir I have mailed you yesterday please check
@mmkr
@mmkr 4 жыл бұрын
Replied. Thanks.
@ravibangaru3484
@ravibangaru3484 2 жыл бұрын
very well explination !! shall you provide all this information through the blog thank you 😊
@mmkr
@mmkr Жыл бұрын
Thanks for the suggestion. I’ll think about it later.
@sainarayana2904
@sainarayana2904 Жыл бұрын
Can u help ...if we add a buffer in clock path for fixing max trans how to check timing paths ..
@kesavakalsikj6103
@kesavakalsikj6103 4 жыл бұрын
Out of this violating for which we have to give priority....can you reply with descending order (include asynchronous checks also)
@mmkr
@mmkr 4 жыл бұрын
Hi, Thank you for watching the video. Ideally the order would be (from the highest to lowest priority): 1. Design Rules (max tran, max cap) 2. Signal Integrity issues such as : Crosstalk, IR drop, Electromigration 3. Timing (setup, hold, recovery, removal, min pulse width, min period etc..) 4. Antenna, and other physical verification related fixes (DRC, LVS, ERC etc..) It’s always better to get the reliable signal first by fixing foundry design rules (like max tran/cap as defined in the .lib models and also any tighter design/frequency dependent constraints if applicable) and the signal integrity issues such as (Crosstalk, IR drop, EM) in the early phases of the implementation, so that the timing analysis is accurate at the first place. But in practical, Timing takes the highest precedence in the back-end flow, although design rule fixing happens (and others) simultaneously. Please note, fixing max tran/cap in the end, might cause hold violations in the design (because most of the times, fixing drvs will help improve the path delay, hence better setup time). In reality, fixing one causes to violate the other. Ultimately it’s an iterative process. So it’s always good to come up with a robust methodology/flow that will help you converge faster and to reduce the turn around time. Hope this gives you some insight. Let me know if you have any questions. Have a good day.
@kesavakalsikj6103
@kesavakalsikj6103 4 жыл бұрын
@@mmkr Thank you
@raveendras4651
@raveendras4651 3 жыл бұрын
How to run STA before PNR, beginner for Physical design, kindly help
@mmkr
@mmkr 3 жыл бұрын
Here is the basic Pre-layout STA flow. 1. Read in the design netlist 2. Read in timing libraries 3. Link the design that you want to check the timing to and make sure there are no linking issues. 4. Source timing constraints (clock definitions, IO constraints, exceptions etc..) 5. Validate inputs 6. Generate timing reports and check your design has any timing violations. Hope it helps.
@meghanavoruganti6753
@meghanavoruganti6753 3 жыл бұрын
Why should we check cross talk at min corners. Please explain.
@mmkr
@mmkr 3 жыл бұрын
Thanks for watching the video. Min corners generally have sharper transitions/slews (when compared to max) and can potentially induce significant noise on the neighbouring nets. If you are still unsure on this, please do an experiment running noise analysis using both min & max corners and see what you find. Thanks.
@krishnanerella2742
@krishnanerella2742 4 жыл бұрын
Hlooo sir, plz do video on Physical cells
@mmkr
@mmkr 4 жыл бұрын
Hi, let me think about this later. Thanks.
@vijayreddy9816
@vijayreddy9816 3 жыл бұрын
Is there any TCL scripting doc
@mmkr
@mmkr 3 жыл бұрын
Could you please drop an email to 8mahe8@gmail.com Thanks.
@alamurisanjeev5126
@alamurisanjeev5126 3 жыл бұрын
@@mmkrdo, How tcl script we use in tool with one example
@vesangisaichaitanya7447
@vesangisaichaitanya7447 3 жыл бұрын
Please make more videos sir on Physical design
@mmkr
@mmkr 3 жыл бұрын
will try!
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