VLSI INTERVIEW QUESTIONS || RTL/ Digital Logic Design questions || Verilog & Digital logic questions

[@ComponentByte]

Hello everyone, My motive behind making this video is to educate you all about the different concepts of digital VLSI Design. I have not discussed the answers of those questions thinking in mind, you all will explore those concepts and enhance your VLSI knowledge. Hope it helps for your better future.

[@tharunsangaraju2780]

Provide answers sir.

[@ComponentByte]

Providing answer was never my intention behind making this video (Don't get me wrong). I have provided enough information. It's now the learners turn to find the answer and enhance their knowledge and skill. I can only tell where to look at and not what are these. Explore the world of VLSI and all the answers will be revealed. Hope you all understand. Thanks.

[@pavan_pelleti]

@@ComponentByte super sir

[@unknowneditz4864]

Looks sufficient to crack any interview, just do this question in a week and you are good to go

[@ComponentByte]

I have tried to provide all the possibility. If any help, I will be always there.

[@unknowneditz4864]

I am going through your Vlsi playlist now, my interview is on Monday thanks brother ☺️. Can you post some videos on static timing analysis and stuff ? Like critical path calculations would be very helpful

[@ComponentByte]

I would have definitely provided atleast some content related to STA but I am out of the place where all my notes are present. From the given link you can get some information if you have not explored it so far. www.vlsi-expert.com/2011/03/static-timing-analysis-sta-basic-timing.html?m=1

[@unknowneditz4864]

Thanks alot very much appreciated will share this channel to all my friends 😊. May I know what you are studying ? Or working in any company

[@ComponentByte]

I was a student, M.Tech VLSI, completed my own m.tech thesis without anyone's help except my best friend GOOGLE. Learned verilog coding during my B.tech and Improved it in my M.tech during my thesis work.Then joined as project engineer (VLSI), improved my vlsi knowledge, learned product development ideas. still believe lot to learn from my youtube channel's comment section. This much. I try not to tell my college name and the places where I worked for some reason.

[@kumarabhisekdas5339]

sir this video was very informative and is very nice to revise the concepts at the end . Please sir can you provide the pdf of these all questions where you have written it.

[@ComponentByte]

You mean questions? If you need questions then please provide me your email id.

[@FPGA_Frontier]

very informative, keep continue.

[@ComponentByte]

Thank you, keep learning.

[@rahulsriram7179]

GOOD ..

[@possibleplus2859]

Was waiting for this 😘 Thank you sir

[@NSHAIKMOTADJANI]

Thank you sir

[@ComponentByte]

Welcome . Happy learning.

[@hyat12]

Nice sir 👍

[@nikitagalar5638]

Thank you sir..

[@ComponentByte]

Welcome.

[@electronics_tune]

It would be great if you provide the solutions for these questions.

[@ComponentByte]

If you have any doubt on any question and want to know the solution then please let me know, I will definitely help.

[@sane4895]

sir can u provide some good question on fsm with explained solution

[@ComponentByte]

Questions with solutions , it's very difficult to find in any website but yes it's available in some VLSI design book but I don't remember the book name. Long back I read this book once . If you explore then you might find the PDF version of it on internet.

[@divyaedupulapati9157]

@@ComponentBytecould u please tell me the book name

[@ComponentByte]

I don't remember the name of the book as it has been long , found in one of a library full of VLSI books.

[@ravisaurav7269]

Sir can provide some vlsi companies to apply

[@ComponentByte]

I have already uploaded a video which includes the name of all most all the company working in the field of VLSI.Thanks.

[@ravisaurav7269]

@@ComponentByte ok sir

[@deepchandmeshineni702]

I think u missed fifo and cache memory bro.. correct me if I wrong thank you

[@ComponentByte]

I have already covered FIFO but not cache memory. What I have covered are the topics related to verilog and digital logic. someone may be asked about cache memory depending on the requirement and mood of interviewer.Thanks.