VLSI - Lecture 7e: Basic Timing Constraints

[@slenderxie]

This is the BEST course I can ever find anywhere online. Very detailed, clearly explained, well outline and very comprehensive. I am Materials Science by education with little EE background. I used to work as fab process/device engineer and now I work as a Product Engineer in a major fabless company. I've been hearing about all those design terminologies (STA, PD, RTL, etc) at work but never fully understand them, and it really impedes my communications with my design and DFT partners. In the past many weeks, I have been learning both of Dr. Teman's Digital Circuits and VLSI Design classes, lecture by lecture, slide by slide, and it's super super enlightening. I wouldn't say I become anywhere close to a VLSI expert, but all these key design concepts now make perfect sense to me, and it is significantly helping my work. Thank you so much, Dr Teman, for providing such great classes online for the public. I cannot thank you enough. Also looking forward to more of your classes in the future.

[@AdiTeman]

Thank you so much for the amazing compliments. I am so happy that my intention is able to pass to people like you as I have envisioned it!

[@arpitsharma3071]

Thanks ! I was unable to understand short path delay for a long time, now I finally get it.

[@AdiTeman]

Great!

[@isaackumba2688]

The course is very clear and helpfull , Few uni did like this course in academia , Thank you so much Sir

[@AdiTeman]

Thank you for the great feedback.

[@rajeshsaha3446]

Helpful lecture.....dear sir your lecture is awesome!!!!! because lectures are very neat and clean theory with beautiful example and motivation.......

[@AdiTeman]

Thanks and welcome

[@akashwayal8797]

sir for hold constraint, the line should be if jitter makes the launch clock "early" we need to subtract it from the data path delay. and not later right ?

[@AdiTeman]

Yes, I think that you got that right. The data is launched early, thereby causing the delay through the launch path to be shorter (the data to reach the arrival point early). The capture clock arrives late, making the capture path longer (slower). Altogether we get 2*Tjitter. That being said, as I mention in the lecture, I believe this is an overkill, since a large part of the jitter (perhaps the majority) is shared between the launch and capture path when a single clock edge is referenced. Therefore, I don't like adding this overhead.

[@akashwayal8797]

@@AdiTeman Got it! Thank you so much

[@bharatnalluri1609]

excellent sir Thank you

[@AdiTeman]

You are most welcome