[VLSI - VERILOG ] verilog code for counter increment by 2 | test bench for counter

implement counter increment by 2 verilog code and test bench
increment by 2 counter
verilog code and testbench for counter increment by 2

[@yaminivanniya7792]

Your teaching was very good . A good teacher gives life to so many students , thank you so much sir. Can u please add your mail I'd in description .

[@VLSI-learnings]

Sure I will

[@mockingbird3809]

Can you please make a video on pipeline addition circuit using verilog?

[@Saath_Chale_toh_Jeetenge]

What a comedy, x and y written in the initial block so we have write reg x and reg y. Why don't you explain like as x and y have to store its current value that is why we have to use reg not nets? All other explanation are fabulous by the way