PD Lec 16- Floor-planning [part-2] | VLSI | Physical Design

[@singhkaptan00]

Sir if we are giving the input to the RTL design do we need to insert ports in the physical design or how will it take the inputs?

[@nhscreations711]

can u plz explain about manufacturing grid in detail

[@VLSIAcademyhub]

Manufacturing grid is the smallest unit level site. In multiple of this grid the shape of block is decided

[@sreemukhi-x7g]

What is the book to follow? He said if we go by book formula for Utilization is as said? Could you please tell us what is the standard book to follow for Placement and routing? and for floorplan also?

[@VLSIAcademyhub]

There is a book on VLSI design by kang, and There's one more book which is widely followed in academics by Jan m rabey

[@bishalghoshb3412]

it's awesome

[@govardhansai4558]

How will come to know the area required for FP to start? How the initial utilization will be decided? How you will decide Aspect Ratio? How you place the port and macro placement? All these without top level information How can we decide...?

[@SocienAsifaShaik]

aspect ratio=Height/Width macros can be placed with the help of flyline analysis

[@karthickramki4062]

I want to learn in cadence tools

[@janapadakannadasongs]

Why we place metal vertical and horizontal ??like m3 vertical and m4 horizontal?

[@janapadakannadasongs]

Yeah..But why we take m4 and m5 alternatively...like m4 only vertical and horizontal we can't take?why we cant?

[@janapadakannadasongs]

@@VLSIAcademyhub i didn't get...my question is why we use alternative metals for vertical and horizontal?

[@SocienAsifaShaik]

To decrease the congestion and crosstalk effect and mainly for better routing density. hope i answered ur question.

[@kishorevalavala9887]

How come the shape is defined? Few are rectangular and few are rectilinear

[@baswarajsghali2074]

Sir, what are routing resources?

[@rajashekarreddy4500]

could you please suggest reference book

[@zunaid4664]

Sir , Could you please check core utilisation formulae once? I think it is ( total core area occupied divided by total core area.)

[@agastinrajece1605]

@@VLSIAcademyhub Core Utilization = (std cell Area + Macro Area) / Die Size Std Cell Utilization = Std Cell Area / (Die Size - Macro Area) my doubt this one is wrong ,,,, pls clarify to me

[@SocienAsifaShaik]

@@agastinrajece1605 utilization Should always be below 70% of the total core area