What is Phase Lock Loop (PLL)? How Phase Lock Loop Works ? PLL Explained

[@ALLABOUTELECTRONICS]

The timestamps for the different topics covered in the video: 0:20 Applications of Phase Lock Loop 1:24 How Phase Lock Loop Works 3:30 Capture Range and Lock Range of PLL 5:11 How Phase detector works? XOR Gate as Phase Detector 9:30 Phase Frequency Detector 13:41 PLL as Frequency Synthesizer

[@108ahah]

Thank you!

[@sss2393]

thank god i found your channel, understood ever bit of it. And you had videos on every topic related to my queries, cant thank you enough, Keep growing

[@hindskn]

Haven’t seen this stuff in years. Very clear. Thank you!

[@frankreiserm.s.8039]

You are a great electrical engineer and teacher. I never understood how an RC circuit could be a resonant circuit, such as in the Wein Bridge. I only understand how LC circuits, with the flywheel effect, can be resonant frequency tank circuits.

[@akhilnandan5516]

RC circuit cannot produce resonance!!

[@alexandermcinnes2313]

Good video explaining the basic components of the PLL, my lecturers literally just assume you get it without explaining anything!

[@denebvegaaltair1146]

Your videos are how I pass my assignments

[@Official-tk3nc]

This channel needs 1 Million subs....Agree??????:):):):)

[@mahnoorsami8623]

Much needed video on speech locked loop

[@agstechnicalsupport]

A really great video on phase locked loops ! Thank you for sharing.

[@francescoavallone-xg7vt]

Thank you very much for your contents. I am a computer engineer with a passion for the electronics and I decided to pursue my career as Firmware engineer. Fortunately with your contents, I am having the opportunity to understand each possible component of a micro. Please, keep going 😀

[@ashwin372]

much better than my college lecturers . College was a waste

[@ashishtayade047]

Thank you sir very nice gide & very nice best information phase lock loop (PLL) teaching video.👍

[@unebonnevie]

Well done on explaining PLL!

[@Vinaykumar-bf8hj]

Awesome explaination ..helped to prepare for interview

[@chandanjain1728]

such a crystal clear explanation sir.thank you

[@Joe-xl8fh]

Excellent demonstration!

[@zardouayassir7359]

The last topic about the frequency synthesizer does not make sense to me. For example, you say that the PLL can be used to divide the input frequency by N. Yet, this requires a frequency divider to be placed before the phase detector. The output of this frequency divider is the same as the output of the PLL. In other words, if I remove the PLL and keep the frequency divided, I can still get a signal whose frequency is divided by N. So, what's the point of the PLL in such a situation ?? Thanks for the explanation though!

[@rohitpathak5313]

Your videos are more informative than my college professor's lecture. Suggestion: You must use a bright and big cursor(bigger than the present one) because it is unable to find at where you are pointing on the screen. 👍

[@ALLABOUTELECTRONICS]

I have already considered that suggestion and now the size of the cursor is increased in the new videos.

[@tomc642]

As always excellent. Phase detectors ate also used in instrumentation. I never could figure how phase sensitive demodulation works when the input is an analog signal, like in signal conditioning for an accelerometer.

[@pravinahshasidharan]

Thank you very much for the clear explanation.

[@nishantsahu11]

very good explanation, thanks for clarifying my doubt

[@saurabhtrivedi6181]

Thanks man, it was very nice and easy to understand :)

[@theonlysiva9547]

Thanks you very much sir, keep doing ece subjects tutorials.

[@AniketB1995]

Really Useful. Thanks for such clear explanation

[@trantien3927]

Very clear video and content. Thanks

[@bangarrajulingampalli1982]

EXCELLENT VIDEO, IT IS EXCITING TO VIEW, KEEP IT UP

[@pro-eq9oy]

Great things I got more knowledge and understand about electronics... Thanks lot

[@hri124]

This was really good explanation! Thanks!

[@jyothico8812]

Thank you for the clear explanation sir!

[@alonsechan8178]

Great explanation, thank you !

[@LightningHelix101]

Do you think there are good empirical models for oscillators? The unsatisfying problem with PLLs is that no one can tell you how to qualify an oscillator’s performance without one. I’m reading through Razavi’s recent book on PLLs now. Jittery is largely incalculable for free-running oscillators. The negative resistance from the feedback devices has a nonlinear Gm moving poles in and out of perfect dampening. The changing bias on capacitors also moves this operating point as well as the dielectric saturates. Reducing the need for the distortable Gm can be accomplished by raising the quality factor of Ls and Cs, but I have yet to find a useful analytic expression for jitter.

[@MrMagic-fc4dn]

I need to know which software u use to create all these schematics and characteristics/graphs :0 Great video!

[@mindf_ckingtruth3395]

At 12:38 you accidently spoke the vive versa if up output is high then output voltage will be pulled up from VDD/2 to VDD.

[@vikramyogan2501]

I also noticed that

[@prajwalbp1087]

Awesome explaination

[@jose421tal1]

Beautiful and clear lecture ! However I see saturating race issue on both FET if the AND gate is slow when both UP and DOWN are High logic. If the and gate is slow, and both UP and DOWN logic are high, there is fraction of time with a short circuit between Vdd to Vss trough saturation of both P_fet to N_fet. I would add to both P_fet and N_fet sources a low value serial resistor like ~50 Ohm to damp the overcurrent in case of any AND gate issue as protection against short circuit and cause possible overstress to fet /damage. Best Regards Jose Tal

[@vikramyogan2501]

Very well explained 👍🏻♥️🙏🏻

[@PradeepKing143]

Increase the size of cursor to clear about where you are explaining exactly

[@youtube-username-placeholder]

A “please” would be nice

[@MrRijubratapal]

Very lucid explanation.

[@ahmetyildiz1306]

master You are the best

[@Parirash123]

Very good explanation. Thank you

[@tony87419]

Excuse me , sir. Is there any wrong with the capture range of PLL at 4:42 I think the center of the capture range is f0 , Please reply , Thanks !

[@rohithrevindran1]

#

[@user-qz6lq4yn8v]

Great really it was needed

[@anoop9416042368]

Thank you so much for this knowledge sharing

[@satirthapaulshyam7769]

So 12:50 ei timee ora freq ta same korbe and phase difference theke jabe but oita constant hoee jabe. It will not cng. Etai amra chaisi phase locked hoi phase diff 0 naile const

[@Yun-bm3iv]

Thank you sir! Could you please make videos about I2C,SPI interfaces?

[@ALLABOUTELECTRONICS]

Yes, soon I will make it.

[@ArjanvanVught]

@@ALLABOUTELECTRONICS Then also EIA-485-A standard and the effect of the resistor terminators in special

[@brandynalbrecht772]

Hey could you do a video on a Delay Locked Loop? With the multiplexers and ring oscillator/ chain system explained?

[@emmannuellendiaye8295]

Mercii beaucoup pour les sous titres en français également

[@gago3001]

I want to follow up on your last example of the frequency multiplier. The f_o is at 10MHz, so the error voltage should be high to increase the f_o frequency. However, the phase detector see that the 2 input signals have the same frequency, so the error voltage should be small. There is a contradiction here. Could you explain further?

[@poojashah6183]

Best👌🏻👌🏻

[@dhirajkumarsahu999]

Thank You, Sir!

[@aryangiri4777]

Sir is there difference in PLL 565 and the one you explained

[@CanQuangTruong]

Hi teacher, I am confused about the capture range and lock range. I suppose that when the input frequency is in the lock range then it can be locked by PLL and now the output of PLL is f_R, if it is out of lock range it is no-lock. Why do we need the captured range because the lock range is enough for PLL?

[@ALLABOUTELECTRONICS]

Lock range comes into picture when the loop is already in the locked condition. The lock range is the range of input frequencies over which the loop can remain in the locked condition. The capture range comes into picture when the loop is not locked. The capture range is the range of input frequencies over which the loop can get locked when it is in unlock condition. Please watch the video from 3:30 onwards. You will get it now.

[@umayaraj7674]

Hi , Is pll is mixed signal circuits?

[@ALLABOUTELECTRONICS]

Yes

[@Suiiiiiiiiiiii.]

thanks u amigo

[@rollis97]

thanks, very good video!

[@bashasaleema6855]

Can you please explain about foster seelay discriminator

[@chethanvenkatesh7901]

Thanks you so much.. PD - averaging of phase difference gave me good insight on PD and PFD

[@LL-ue3ek]

It's somewhat straight forward to lock two square waves. But is there a known way to lock two sine waves?

[@lauraaconceptslk]

what is the use of the feedback divider?

[@emilcalilov8910]

Thanks, amazing. Do you have videos on flip flop, clock signals etc?

[@ALLABOUTELECTRONICS]

No it is yet to be covered on the channel.

[@hydrogenkhan8728]

Good job. You are a good teacher and real "Gandoo"

[@gago3001]

so when the PLL is locked, the phase and frequency difference is minimized -> the error voltage will be minimized -> how can the f_o can increase to meet f_in?

[@lwalida8905]

Thank you so much my friend

[@te9781]

Something really driving me insane !! If we used PLL in AM demodulation receiver ..in the PLL mixer the AM signal multiply by fc after the LPF output the subtraction will give the information signal which is not a zero value of constant voltage if local fc not matching received fc

[@KRISRONIN]

SIR CAN U SEPARATELY MAKE A VDEO ABOUT PHASE SHIFT I CANT UNDERSTAND

[@Crazyforelectronics]

can we connect nmos instead of pmos

[@Opticx25]

Thank you soo much sir

[@mahnoorsami8623]

Can u expllain in video speech locked loop method

[@ajingolk7716]

Capture range and Lock range?

[@prakash-r1k]

can i increase the pico rp2040 freq with pll

[@Benny332187]

Can I get a Power Point or PDF File of this video?

[@erfan_zar]

Awesome!!!!Thanks

[@ManojKumar-jw5ys]

THANK YOU BUDDY !!

[@ArjanvanVught]

Thank you!

[@rakeshshrivastava4249]

Thanks, very nice,

[@ramalakshmikola1652]

Plz..provide the derivation....deltapi=0

[@friosminsysnym]

Technical wise no problem, but still don’t know why the applications use PLL

[@GauravGupta-pb8mk]

Thank you sir

[@notchskills7897]

Thanks so much

[@Shiny_Mewtwo]

Thank you

[@TELEZUD]

Super! Thanks!

[@GokulGokul-iz2to]

Thank u sir

[@АндрейПетров-е8ц4у]

Nice.

[@zinhaboussi]

nice

[@Vishalkumar-mu5hy]

Who is here after lookin a radio review.

[@lovely_ji]

No one,, and u need to grow up 🙄

[@mahantheshasmahantheshas8509]

❤❤❤

[@rishitgome2073]

Oh! wrong pll

[@bharanidharan3510]

Sir can I have your number I need your help for our project sir

[@princyjoseph3408]

Thank you