What is wrong with 5nm, 3nm, 1nm.. CPU Technology Nodes explained

In this video I discuss modern Process Nodes and explain why smaller transistors are faster and more power efficient. Why nm matter? And should you believe CPU marketing?
#nanometers #processnodes #transistors
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[@AnastasiInTech]

Let me know what you think !

[@ManyHeavens42]

Your the best ,All rolled into One!

[@harishmanitiwari5935]

YOU ARE LOVE 💕

[@jkn6644]

Somebody should start comparing nodes with transistor density.

[@damianmasalias9242]

Pienso que eres HERMOSA!!!!

[@masternobody1896]

i want -1 nm cpu for best gaming performance

[@pacifico4999]

I've seen too many people comparing nm directly and saying Intel is far behind, it's great to hear an actual explanation. I also love to see that as we reach atomic scale, engineers need to be creative and change the geometry of the transistor. From planar to FinFET, to Gate All Around and more.

[@kayakMike1000]

Geometry at atomic scales gets really murky. You're in a realm where Heisenberg's uncertainty principle starts to make any geometry into a probability field... Then again, atomic scale transistors can't work with n type and p type semiconductors as the n type and p type properties are emergent properties of silicone crystals with a few impurities, so... That's at least many hundreds of atoms if not more. I'm not sure when those emergent properties from the impurities would lead to normal transistor operation.

[@RA-II]

You right.

[@BBBrasil]

I was thinking about the atomic scale of the chip designs, never made a move to check it out. How can we print UV etched circuits so small? Certainly Heisenberg wouldn't allow that. Interesting to see planar going 3D 🙂 Loved the video.

[@DFPercush]

Maybe a dumb question, but if the gate completely surrounds the substrate, where do the charge carriers go when the field is applied? Is there some kind of skin effect going on? Cause planar FETs push the charges to one side creating a channel near the gate. Those carriers need a place to escape to create a depletion zone.

[@kayakMike1000]

@@BBBrasil I bet tech might exist to manufacture truely atomic scales using electron tunneling microscopes, but it would take eons to build a single chip. EUV is needed to build at reasonable time frames.

[@eaaeeeea]

They should go for transistor count per square or cubic micrometer. Would be the easiest to undrerstand for everyone, and would be more telling of the actual performance. And as a bonus, it would rise continuously as technology progresses.

[@FictionalEngineer]

Yess, its a good idea.

[@H53.]

So... Intel should take advice from a YT comment. Got you.

[@arcanicful]

@@H53. agree, not even best advice can help them now.

[@edwardduda4222]

You’d already know what it means if you have a computer science background or if it’s relevant to your profession. Most normal people don’t care about specs, they care about price which usually corresponds to the chip model age and performance.

[@dayvie9517]

​​​@@H53. Actually no. This would describe an industry standard for creating specs. It would be for everyone, not just Intel. It would make less sense otherwise (nothing to compare, so why list).

[@lachlanc.3509]

As a student/researcher with more of an analog/RF background (as opposed to digital like CPU/GPU), the main benefit of technology scaling is increased cutoff frequency. It is the frequency at which the transistor provides unity current gain. Cutoff frequency is a function of transconductance (gm) and parasitic capacitance (mostly Cgs and Cgd). Above this frequency the transistor stops acting like an amplifier. For example, TSMC 180nm has a cutoff frequency of approximately 50GHz meaning that it is not practical to make analog/RF circuits that operate at or near this frequency. The cutoff frequency of CMOS devices continued to increase with technology scaling until 22nm when the cutoff frequency peaked at around 350GHz. In fact, newer nodes like 16nm,10nm,7,etc. have cutoff frequencies significantly lower than 22nm. FinFET transistors have good density for digital circuits but the complex geometry adds undesirable parasitics at high frequencies. Chip are most commonly made in CMOS but other materials like GaAs or InP have carrier mobility that far exceeds that of CMOS, leading to much faster transistors and better analog/RF qualities. Although non-CMOS technologies are far less dense (like 100K transistors/mm^2 instead of 100M/mm^2). Perhaps heterogenous integration will be necessary in the future to continue improving analog/RF performance. You could have the density and Moore's law scaling of CMOS with III-V transistors for RF that have very good high speed performance.

[@AnastasiInTech]

Lachlan, thank you for your comment. Indeed FinFet is not really made for RF and even more not suitable for mm-wave applications, for reasons that you mentioned and also for cost. Most of RF/mm-Wave circuits do not scale with tech nodes and thus getting more and more expensive with each tech shrink. 22nm CMOS will likely be the RF sweet spot for the next decade. On the other hand we will see more CMOS + III-V integrations in e.g. SiP for those RF/mm-Wave applications where RF power is important.

[@MarvinHartmann452]

Very interesting. I'm only a technician but would I had the choice, it's something that I would have like to study more. But I'm too old now, so I watch these videos instead and try to learn as much as I can. Also, english isn't my language.

[@gordonlawrence1448]

There are still a few NMOS and TTL devices. Believe it or not some new designs are still using the 8051!. Not the 80C51 the actual 8051 with EPROM.

[@Krzys6301]

Your input is just extraordinary. Thank you for sharing this.

[@josephlee4337]

​@@MarvinHartmann452 You are the only one . I am also in your status. I don't know what is your story, but me, I wasted my life away. The only thing I can do now is to learn as much I can to satisfy my curiosity. Good luck to you, sir.

[@LinuxJediMaster]

This is by far, IMO, the best electronics technology channel on YT. I often find myself thinking "oh she just covered a point I was wondering about". Anastasi explanations are brief and concise, but packed full of information; it is like her content is the exact opposite of "fluff". Plus to top it off (not that it has any bearing on these subjects) obviously she is absolutely gorgeous .

[@billgates3699]

This was the boomer post I was looking for. Didn't have to scroll far 😂

[@MikkoRantalainen]

I hope the industry moves to transistors per square millimeter sooner than later. That's a measurement that doesn't allow the marketing department to get too creative. It also directly tells the usable transistor count instead of some measurement that cannot be interpolated over big areas.

[@miguelJsesma]

I really though that nm was a real measure for transistors, but your explanation makes much more sense. Thanks Anastasi.

[@terjeoseberg990]

Once the technology became physically too small to actually make for real, they switched to imaginary “equivalent” measurements.

[@DarthAwar]

That really stopped at 24nm but even before than many 48nm or smaller nodes where often more an average or guess than actual transistor size!

[@terjeoseberg990]

@@DarthAwar, Right.

[@rdwatson]

Great overview. The numbers are still useful for comparing different chips from the same manufacturer, but not for other manufacturers.

[@sanaayassin5712]

By by by by Dr Dr see we

[@thehobe150]

This is an excellent review of the present fine pitch semiconductor processes. As a retired Analog design engineer, this was a better explanation of many nanometer numbers thrown out by the marketing departments of semiconductor suppliers. Very good graphics as well!

[@AnastasiInTech]

Thank you 😊

[@Sandra-sv3ow]

Thank you Anastasia for your great videos. I have watched all of them and can't wait until you have the next one up!

[@AnastasiInTech]

Thank you 😀

[@CommodoreGreg]

Anastasi, your subject matter expertise and passion really resonates with how I think and where my interests are. Fantastic channel. Thank you and please don't change!

[@wucwug]

Anastasi, this is an awesome video because the graphics you used enchanced your explanation greatly. You arrange the flow of the topics very systematically. I was a semicond equipment engineer. I'm amazed by the simplicity of your naration and explained to the comprehension of the lowest assisible knowledge in the field. wow.. congratulations! great job!!

[@AnastasiInTech]

Thanks a lot😊😊

[@crhu319]

Yes I'm constantly forwarding her explanations of computing hardware issues to people who get facts from liars or idiots like Peter Zeihan.

[@eramorn]

Thank you Anastasi! Like always you are delivering absolutely great content for us to watch. 👍

[@abhisheksarkar2151]

Hi Anastasi! As a bachelor student of Electronics, I cannot thank you enough for this video. I had tried searching for information and distinction on the technology nodes in many books, videos, papers and webpages, but this is where I understood it fully. Thanks!

[@razoraz]

Amazing that this video is promoted to me by youtube a year after it was released. A sign of quality content. When I was a kid in the 90's I somehow got intel to send me technical manuals about it's latest CPUs... I thought they were cool but above my head. Well I ended up in software/web development at age 16 and since but I've always been fascinated by the silicon innovations underneath. Thank you Anastasia for giving us a peek into the physics of it all.

[@razoraz]

Sorry if I misspelled your name too, despite knowing the greek root of it means "resurrection". Just putting it out there; "dead" languages are still useful to know!

[@NamiduIndunel]

Excellent, after all these years i got a real idea about this. Thank you.

[@InnerFire6213]

The microprocessor industry is nothing short of magical. You can explain it down to the lowest details but in the end you just have to accept how it simply works. Like how billions of transistors can produce a computational task. It truly takes an incredible mind for anyone to be working in designing these chips. This is the pinnacle of human ingenuity

[@kakistocracyusa]

"Architects" and managers do not design the chips, the process/materials physicists/engineers who elect to pursue and open up the pre-existing design options do. The many 3D geometries have been around for a couple decades.

[@InnerFire6213]

@@kakistocracyusa huh? where did i say that architects and managers design the chips?

[@kakistocracyusa]

@@InnerFire6213 The structural design of chip circuits is commonly referred to as "chip architecture"

[@InnerFire6213]

@@kakistocracyusa i don't know why you feel like you have to tell me that but thanks

[@tigertiger1699]

🙏🙏🙏🙏🙏🙏 with 45 years in heavy & marine engineering also production machining.., I have but some appreciation of your industry and the accuracy & precision…., it blows my tiny mind…👍🙏🙏🙏 And you are so youndg👍

[@MatteuskVlog]

I would love to see a video explaining and comparing different gate types what are used. Like apple m1 chip, amd ryzen and nvidia gpu gates if they have similiar or different gate types and how it affects batterylife and powerconsumption. Love your videos, style of the videos and overall feeling🤘🏼

[@Joe-Dead]

that, and why the newer smaller nodes nvidia and some others are using are doubling or more in power consumption. is there a limit of sorts where power saving ends/no longer scales as it did due to issues with the nodes getting so close to that quantum limit?

[@terjeoseberg990]

@@Joe-Dead, The power used is proportional to the number of transistors, the capacitance of each transistors and the clock rate. The capacitance of each transistor is related to the physical size of the transistor. It used to be as the number of transistors per chip increased, the size of each transistor decreased. As explained in this video, this is no longer the case. Now, as the number of transistors per chip increases, the size of the transistors grow in the vertical direction so that the actual size of the transistors doesn’t shrink.

[@Joe-Dead]

@@terjeoseberg990 that doesn't actually answer anything. smaller process nodes have TRADITIONALLY shown an increase in efficiency. IE, less power used and less power wasted as heat. then you have nvidia using tsmcs smallest nodes and DOUBLING power consumption. it's not just more transistors, i know how that works...pretty obvious more parts = more power needed. even with the savings from efficiency using smaller nodes. while the power draw was going down it went WAY up. you'd expect that kind of doubling if they doubled the amount of transistors as well...well doubled and added a bit more since you have to count for efficiency from smaller nodes as past node changes had produced that efficiency at an almost predictable scaling. one thing you did not mention and i felt i had no need to...the power consumption could just be down to how they designed it...but why would you design such an absolute power hog? when the trend has been towards efficiency? sipping instead of mainlining current.

[@terjeoseberg990]

@@Joe-Dead, Actually, my answer does answer the question. You obviously don’t understand it. The capacitance of a transistor increases with the size of the transistors because the transistor looks like a tiny capacitor. And if the capacitance is greater, it takes more current to switch the transistor on or off. It also switches slower. That’s why the clock rates stopped increasing and why the power usage has increased. There is no longer a reduction in capacitance and therefore current with smaller node technology because the transistors are no longer getting smaller.

[@terjeoseberg990]

@@Joe-Dead, If you don’t understand what I’m saying, watch this video again. She explains what I’m saying in this video. The transistors might be getting narrower, but they are simultaneously getting taller, and therefore they are not getting smaller.

[@BrianThomas]

I had no idea. Thank you for clearing this up. It really makes a lot of sense now.

[@pulgamecanica]

Anastasi! You are one of the most insightful people I've seen on the internet and your videos are very well made! Congratulations and keep it up!

[@gropatapouf5998]

I am totally clueless when it comes to the inner circuits of machines and yet I understood most of your explanations. You're great I hope you're a teacher, thanks for your work!

[@h069401]

I like how you always have the mic in shot. Lends depth. Great work. I'm a fan

[@dbs2132]

Amazing explanation.. no one can explain this simple this complex technology! Great work👏

[@vineetkumarbharti2633]

Great explanation as always. Idea for another video : explaining how logic density differs from SRAM/cache and Analog/( I/O) density from different manufacturers as well. Also multiple layers of EUV and MASK. Also core to core interconnect like ring or mesh formation effecting power consumption. Like even on Intel7 Intel chip using 50% more power than AMD on 7nm. Last but not least, manufacturing of DRAM and VRAM, why they are stuck on 10nm. Thanks!

[@le-berry]

I certainly enjoyed your expertise and presentation in a technical but understandable manner. Loved it !!!

[@konradzuk6303]

It is always good to put low pass filter on "vocal" stream and also cut some excessive high mids frequencies with equalizer to make speech more accessible to the listener... tons of information from this great channel are worth it

[@dosdoktor]

She cuts mids and hi's, speaks like whispering, I resemble transsexual voice features, breaking in the process the male/female recognition system of a brain rated IQ 160. Now, the question is (I know it sounds cheeky and undesirable): "Anastasi in Tech" is a he or she?

[@loverschoice885]

haha i was thinking the same, but, i dunno, theres something with tech and a lot of sssssssssssssssssssssssss´s thats relaxing.

[@konradzuk9661]

@@dosdoktor of course it is nice and very inteligent girl, there might be an issue with vocal cords/larynx it happens.. Great channel, she is really "horny" on hi tech... I mean it's her real passion, I admire her :)

[@konradzuk9661]

@@loverschoice885 are you a ASMR fan? 😅

[@Fogmeister]

Amazing! Thank you for doing this!!!

[@mradminus]

Just found your channel, very interesting, please keep it up. For the first time I understand a little bit better how finfet transistors work.

[@pixelfairy]

Reminds me of led light bulbs. A "60 watt equivalent" might only draw 5 watts.

[@leadiususa7394]

Great job presenting this! Keep it up...

[@odebroqueville]

Wow! I had no idea the dimension had just become a marketing gimmick! I hope you'll make a video explaining what IBM's analog AI chips are and how they work. Thank you, Anastasi.

[@wadz668]

I've watched so many videos on this very topic and THIS video is the one that explains it in a way I understand. Thanks for the amazing video!

[@ThomasLee123]

Being a guy with military background, I am interested in how transistors used in modern IC gates respond to EMP attacks. Back in the early days it was discovered that cmos gates in integrated circuits were susceptible to damage in high voltage situations such as static where very low current is found with very high voltage. I'm wondering if the military transistors have found ways of getting around EMP attacks as transistors have become smaller and smaller, eventually breaking the 1nm barrier. The only way i know of is to use TTL instead of FETs,

[@thecraggrat]

CMOS has been rad hard for over 40 years...back in the 80's, and still today, rad hard devices were made on SOS wafers. A SOS wafer has a wafers made of sapphire and an episilicon layer deposited on the top surface. The active trasistor regions are defined in the epi layer and there is no connection between the p and n channel areas to allow for lockup. Buried oxide layers like AMD used also produced the same effect, not sure about the TSMC process. Another way of producing rad hard devices is to implant highly doped buried layers that 'sweep" and current from an ionising event away from the transistor areas to junctions where the charges can recombine safely. BTW here are a couple of papers that detail EMP effects, if you are interested: www.researchgate.net/publication/310582078_Latch_up_effect_under_electromagnetic_pulse www.researchgate.net/publication/296683413_The_Induced_Physical_Effects_on_the_Semiconductor_Electronics_under_Electromagnetic_Pulse You can download the full paper.

[@gb-channel1880]

Thank you for the explanation! I remember the spec race in Hi-Fi equipment by Japanese companies vs NAD musical output from music medium like Vinyl,CD, Cassette. Maybe that was a bad comparison but I was thinking according to marketing process to sell products. Yes , I use NAD Audio devices.

[@MarvinHartmann452]

You surely remember the power war of the late 70s/early 80s, too. I used to have many different brands of systems. I do like Nad. I think m Mcintosh also makes awesome systems, Accuphase is quite good, too. There's so many of them that are good.

[@sebassanchezc-1379]

I would never knew about this without your videos. THANKS😋

[@SergiMedina]

Most interesting, especially where you explain in detail about the nanometer debacle, which many people unfortunately still confuses! You're beautiful, thanks!

[@jpprivatechannel7381]

Your videos are very very good! Very informative and clear!

[@springwoodcottage4248]

Super interesting! The marketing folk had confused me, but I like to look at power in & performance out which makes me immune to a lot of the marketing. Still lovely to get more clarity & information. Thank you for sharing!

[@totoliciu]

Great video and great way of explaining very difficult things! You are very intelligent and congratulations for the idea!

[@RalphDratman]

Excellent, thank you Anastasi. Where is your discussion of vertical transistors?

[@AnastasiInTech]

Here: kzbin.info/www/bejne/f3nbp2ubnderaLM

[@GregoryShtevensh]

Awesome video! this is the 1st time I discovered your channel... Your voice is lovely and your explanation was thorough! subscribed

[@benmcreynolds8581]

I know you mostly cover the "hardware" side of things BUT would you ever consider doing a video covering: Where we are at with our ability running physics simulations? I really find physics rendering so facinating and I'd enjoy anything covering physics based advancements or creative ideas related to this topic.

[@Av-fn5wx]

1:05 "Those are tiny, but very powerful guys". Not sure why, but it boosted my confidence a bit.

[@JonS]

Even for planar transistors, the nodes stopped being referred to as the minimum drawn (polysilicon) geometry. I think it was around 0.25um where sideways diffusion started being considered, leading to stated gate lengths that were smaller than the drawn length (which is actually fair). Is your cat a British Blue (Shorthair)?

[@thecraggrat]

Yes you get lateral diffusion of the S/D dopant, but the technology node was referred to by the actual design size of the gate electrode down to at least 65 nm, I say at least as I skipped the rest of the planar nodes to 22nm FinFET. The actual size of the transistor at any given node may have slightly different to the target size to get the transistor characteristics on target. So a nominally designed 130 nm transistor might have run at 125 nm to get the characteristics correct... Actually looking at what I wrote above, I think I should expand on the subject... You are actually correct about the lateral dopant diffusion, & what I said was true of where I worked, some companies though would label their technology node based on Leff, the effective length of the gate/channel (or you could say the electrical length of the channel). Now there are spacers along the edge of the gates that make for a more gradual doping variation & hence electric field at the gate edge to stop hot electron effects, but that is another story. Looking up a cross sectional analysis of TSMC 28nm process shows LP PMOS transistors are 29.8nm, the HP PMOS are 25.5nm**; TSMC seem to be using a standard fabrication of the LP transistor and a poly fill/planarisation fabrication for the HP process, so you can see how the transistor electrode can 1) Be different sizes depending on the requirements of the transistor and 2) Fabricated differently. This is at the same nominal technology node... Again you can see this here if you are interested: www.techinsights.com/blog/review-tsmc-28-nm-process-technology **TBH, the structure of this transistor is not obvious, it could be as large as 34nm, in fact this may be more likely, with the gate electrode as a tri layer of maybe TiN/W/poly fill - I'm guessing based on the crystal structures...

[@revcrussell]

"Taken over by marketing guys." That is cringe to every engineer. I think of the Dilbert TV episode _The Competition_ .

[@CommodoreGreg]

It's cringe to consumers too.

[@harryv6147]

Anastasi in tech, Very nice explanation of the details of the various benefits of the size of gates an various thickness effecting capacitance and therefore switching frequencies! Nice tech talk and well presented! I love your Italian/ Austrian accent is actually is pleasant to my American ear. I have subscribed and watch your other posted videos! I was wondering what school you did your studies! Obviously, you are doing quite well in the field! Marketing is evolved with sales besides engineering and have different motivation and direction!

[@EulerFink]

In my ingenuity, I was thinking "oh, the nanometer in the nodes is the precision that they can create every part of the transistor " but now I know that I completed misunderstood everything.

[@xila8861]

Amazing Video, Thanks!

[@jaspertell3970]

finally a proper explanation of nm vs design / density, cute kitty and wine glass water was a fun touch, well done

[@jamesdubben3687]

Great explanation, thank you. How do they get the rectangular "chips" out of those round disks?

[@chrisheath2637]

There are thousands of tiny "rectangles" on 1 large disc - you can sometimes make out the little rectangles on the videos...which can be CPUs, GPUs, memory chips etc...

[@AnastasiInTech]

Hi James, check out this video 👌 kzbin.info/www/bejne/fZqVqJ6Hdryth68

[@gauravtank5664]

She has Voice thickness of 1 Nano Meter! Directly touching to My Heart! ❤

[@davidwalterhughes2258]

Thanks for all your work ;)

[@EdgarPoe_Raven]

You have earned my subscription. Thank you for the content.

[@xenthia]

Your voice is sooo soothing, perfect for the subject. Liked and subbed.

[@Piotrek1985]

Very informative video. Thank you!

[@practicalengineering2374]

I love u so much your generosity and simplicity

[@brute_force_and_ignorance]

Since the interconnect delay is starting to dominate the switching time, packing transistors closer together will continue to reduce the interconnect delay time portion of the overall switching time, but the increase in physical size of the 3D transistors might make that a wash.

[@MrEddieLomax]

Well, as a chip designer it has been 'routing>logic' delay since going below 1um. So 3D transistors halving routing delay would be a massive advantage, I see a future where the transistor could get larger but stacked three layers deep, the biggest problem then becomes heat...

[@warrenbosch3581]

Thank you for this excellent understandable presentation! Question: How does node size and production yield correlate to reliability for the end user? Thanks!

[@swisstraeng]

Well, brands aim to keep a certain level of reliability. If we were to make larger node with nowaday's precision, sure, we would have better reliability. It's all in balance.

[@kazedcat]

Reliability is not correlated. Reliability is more a factor of binning. Chip die have somewhat random quality so they sort them and lower quality chips are sold as lower end product. This lower end product has reduce performance by lowering clock and source voltage so even though they are lower quality their reliability actually improve because the silicon is not driven as hard as the top performing chips. The top performing chips is driven to their redline but since the silicon quality is better reliability is still good. Unless the product vendor decides to drive them pass their redline so that they can catch up to their competitors top performance. That is when reliability becomes an issue

[@holmybeer]

A dumb question. Do CHIP internal wiring downscales too? Doesn't it affects resistivity? Since ohm's second law states that resistivity is inversely proportional to conductor's cross section, decreasing it's thickness don't create more resistivity? Or it balance ou, since we have less current going though the wire? What am I missing? Btw. Great vídeo, thanks for the solid work

[@AnastasiInTech]

Yes, good point! It scales down too, but not at incredible rates. The thinner the wire, the higher the resistivity for a fixed length… that’s the issue with interconnect I mentioned in the video. Speed is mostly limited by interconnect parasitics..

[@listerdave1240]

But also apart from having less current flowing the resistance is proportional to length. If the transistors are smaller they are closer to each other so the interconnects are shorter. I would think also the interconnects can be made thicker in the vertical direction to compensate for the reduction in width so they are like in the form of a tape.

[@BBBrasil]

@@listerdave1240 Good solution for the parasitic, too. Is it cost a factor here? Or the extra steps?

[@thecraggrat]

@@AnastasiInTech Please, resistivity is a property of the material, resistance is something that you change with geometry. Thicker films have less resistance for a given line width (more area). In process resistances are usually measured in ohms/square for films, or ohms for a structure.

[@donaldj5317]

One of the best common explanation to Nano technology

[@user-ef5ok8ox8r]

Terrific videos, thank you for sharing these with the world!

[@williambreeze2659]

Thanks for the video!

[@cooperfeld]

If gate length is not expressive anymore, I'd switch to transistor density (transistors per square mm for example). Further minimizing of structures amplifies the problem of leakage currents, quantum noise/tunneling effects and high frequency interference. With focus on the first aspect, shrinking down only helps if efficiency raises in the same scale. When facing current GPU development (take RTX 10xx to 40xx series) in terms of power consumption, it seems half of the electrical energy dissipates through leakage already - manufacturers move towards producing overpriced power resistors, so to say. To conclude, at 5 nm we might approach the rational limit for Silicon-based chip technology - we're talking about the width of 50 atoms btw. For more downsizing towards 1 nm and below, let's rather find better materials and production technologies.

[@davidwalterhughes2258]

Your videos keep me excited to be creative and give me ideas for new inventions for the near future. Thanks for the inspiration

[@sonofamortician]

always love your explanations, thank you

[@AnastasiInTech]

Thank you ☺️

[@sharanpaulsinku1096]

Learned something new today, thanks 🤓

[@cyberkiller83]

Enter for the info, stay for the voice!

[@abhir7823]

Thumbnail made me wonder why a shampoo ad was mentioning computer chips

[@kelvinkoay3729]

Hi Anastasi, first of all ..... Thank you so much for this great information that quenches most laymen's curiosity about wafers especially on the nanometer terms... Thank you so much... 2nd of all, you are so beautiful yet so intelligent! Thank you so much for this contribution into this complexed semiconductor world.

[@freelunchforchildren4040]

I was an analog design engineer in the 80's

[@volkerball3]

Hello. This video was really good if somebody would like to a know a little bit more from process nodes. You've made a little mistake. Originally a process node as you told, showed that how long the gate in the actual transistor. But much more before FINFETS there was a little change. In 1997 or 1998 when Intel moved from 350nm node to the 250nm node. At the 250nm node the gate lenght was much smaller (190-200nm) because the engineers dircovered a method how to shink it's size more smaller than other parts. And from that node until the 32nm (Intel's last Planar FET node) it was defined also something else. A measure was adverts to a size of a group of transistors. Anyway your videos are real good. I'm impressed. (I've first seen TSMC - ASML ) And your hair is really nice. ;)

[@NotGeraltofRivia]

Thank you Anastasi!

[@perfectlycontent64]

Great summary thank you. I wasn't aware of that gate thickness was already reaching quantum mechanical limitations (30A), and that this would slow down gains in power efficiency.

[@tstager1978]

Great video. Excellent explanation.

[@ce9916]

Amazing content as always. What is the name of the song that plays at the end please?

[@TheJubess]

Came for your amazing hair(you could easily have this sponsored by a hairproduct brand), stayed for the information. So clear of an explanation! Thank you

[@crhu319]

Hair is advanced girl technology. We can't understand. No video can explain it.

[@cesargermanmorteo8403]

Wooow I admit that i love your content is great !!

[@__--JY-Moe--__]

I'll be glad to see the linear, stand-up & applaud!!

[@rolflandale2565]

Nothing gets as impressive than the 7:59 😻 *switching speed*

[@DigitalDesignET]

Just love how she explains technology, thanks

[@bazukamimi5721]

Perfect explanation, especially charging the gates

[@agoodun]

Very good video. Excellent explanation and breakdown of complex ideas to easily understandable terms for a normie like me. Lol. Thanks.

[@shahin8569]

Thank you this video was really informative and useful for us ♥️♥️thanks for you'r time

[@gagandeepsingh8069]

very insightful. this was very knowledgeable and informational video in such short duration. Thank you.

[@Electrowave]

It's amazing how tech has progressed over the years. Thank you for your wonderful explanation, it makes modern computer technology easier to understand for an oldie like me :-)

[@paulo..ferreira]

Given this great explanation, I think what we should focus really as costumers is the performance x price and performance x power consumption.

[@MrFoxRobert]

Thank you!

[@Ohem1]

I'm more occupied with the thought after 1nm when we reach picometers. Is that when we have to turn to quantum computing or are the other solutions in terms of efficiency?

[@pacobrezel]

Nice and interesting "deep dive"! What is your opion about chips based on other physical principals like light?

[@AnastasiInTech]

kzbin.info/www/bejne/gmfSiXScq9J9h5o 👌

[@pacobrezel]

@@AnastasiInTech Thanks!⚡

[@pacobrezel]

@@AnastasiInTech Here some deeper dives on optical chips (:-D kzbin.info/www/bejne/eYbZhn1rgdOqnLs kzbin.info/www/bejne/rGjMcqSZe6iHh7M kzbin.info/www/bejne/i4iwdn6brZuhj6M kzbin.info/www/bejne/poSUq3R3eZahjqs

[@kellymoses8566]

Spintronics has a lot of promise

[@indrashispowali]

@AnastasiInTech From where have you got the processing and in-fab videos?

[@StefanoFinocchiaro]

I think that transistor density should be used instead of nm

[@kellymoses8566]

Yes, transistors per square millimeter is directly comparable between companies

[@Zisopoulos]

I've turned on my Mackintosh Plus in virtual flopy drive mode, while watching this episode :p Thank you for knowledge you give Anastasia (ΑΝΑΣΤΑΣΙΑ) :-)

[@lokvid]

Thank you for clarifying the meaning of these numbers. I was always wondering if they are some measure of the density. But obviously they are not.

[@thecraggrat]

Pitch is the usual measurement of the density, ie how close together pairs are. For example true dense is equal line & space, if you can build transistors that close together they are really dense. You might only be able to print them, say 2x the line size, so a 100nm transistor can only be placed every 200nm. That is a simplistic and sort of unrealistic explanation but gives you a good idea. Also the smallest pitch of backend metal connections has a big impact on how large the die is, it isn't just what you can do at the transistor layer...

[@pablolarraguibel]

Muy buena explicación!

[@ErickAlex1]

I love the content here! Feedback: is there a way to change the microphone/ audio settings so there is not too much treble? The letter S sounds extremely low while the rest of vocalizations are 3x lower? Its minor but it would help the overall sound quality…

[@emiel333]

Great video and you’ve got a sweet voice 😊

[@nathanmoses1953]

Thanks for the explanation. I was wondering how they were managing to push gate width below about 7 nm.

[@MarvinHartmann452]

So, the smaller they are, the higher the bandwidth, the lower the voltage. Interesting, it makes sense. I'm only a electronic technician, I'm not a mega genius like the people this video is directed to, but it's very interesting.

[@stefanopilone957]

Thank You, I am wondering how it is possible to have image of vertical section (for example at 8:48)