What's the need of CASE ? | Lets Learn Verilog with real-time Practice with Me | Day 16

[@ivogaycaramuti1243]

very usefull

[@gayatri5397]

Inside the always block a reg type can be used right but in this case you are using wire type as the ports are wire type, I am talking about sel, sel inside case should also be reg right?, would that not be an issue? pls explain, thanks

[@anandbvs143]

Nice

[@goodn1051]

would you mind shedding light on applications of these tutorial in the outside world, where the industry is headed at the moment?

[@goodn1051]

enjoying these series btw...complete god sent

[@whyRD]

Yes sure , these are fundamental problems and any high tech complex circuit have first step as these fundamental problems only