Why casex/casez | Lets Learn Verilog with real-time Practice with Me | Day 17

[@PilatesinSacramento]

I'd second the comment below. It seems as though casez accounts for if an input is 'z' which is floating and 'x' would be broader which would account for 'z', 'x' or 1 or 0. In the exercise on HDLBits, there is nothing saying that an input could be floating. I'd assume that all 8 inputs are being driven to valid 1 or 0 values. Anyway, thank you for another great video. I'm moving along through them and enjoying it!

[@S_R911]

keep going bro ...Lots of love . I am not missing even a single video of yours...

[@nityanand4581]

Please elaborate more on casex vs casez. i am confused after reading from lot of sources. Synthesis vs sim diff and why casez is better

[@nimmanashashankkrishna6114]

why is the hdl site not working

[@tanuraj1928]

I think msb bit should be taken as priority bit not lsb bit. Correct me if i am wrong

[@ivogaycaramuti1243]

very useful video

[@anandbvs143]

Nice

[@EE23M112MdAli]

a=0 b=0