When to Apply Thermal Relief Pads to Your PCB

[@ninadtaralekar]

Thank you for the great details and explanations on designing parameters 👍

[@petersage5157]

Thanks for addressing this; I was one of the people who mentioned this in a previous video. Obvious exception is obvious: If your pad or pin is to sink heat in operation, donut relief. ECG862 ground pins, for example, could desolder in operation if there is thermal relief and you don't have any other heat sink on the chip.

[@Jimji-qr4fi]

Thanks Zach, I enjoy your videos! I just wanted to mention IPC 2221 has a calculation for the tie width = 60% of the diameter of the ideal pad, divided by the number of ties per layer and 4mm combined across every layer. Here is an extreme case, but the company I work at uses this rule as we have some design where we didn't use this rule and and they had many layers and 2 Oz copper. When Hasl finish was applied they struggled to get the middle of the PTH hot enough for the HASL to flow in there and lead to poor solder flow and corrosion problems. Thermal relief and preheating fixed those issues. Also hand soldering those pins on the connector required know which pins were a plane connection and trace. They would over size the iron for the plane, but if they soldered the trace pins with the same iron, it would damage the pin trace internal connection. I think it is worthwhile to be selective in which layers are used and by how big a tie needs to be so you don't go over the 4mm rule. Sometimes we still need to make a compromise. Too thin a tie and they might open under high current.

[@jimjjewett]

To clarify, does that mean a maximum (combined) connection width of 60% diameter (so less than 1/5 of the circumference for a round pad) on any single layer, and a maximum connection width (per via) of 4mm combined across all ties on all layers?

[@Jimji-qr4fi]

@@jimjjewett correct, and the circumference isn't taken into account. For vias I don't thermally relief them. Sometimes you will still want to bury pads for therma or rf reasons. I use vapour phase soldering which is good to solder buried pads, but makes rework or hand soldering much harder.

[@saeedkizzy]

Thanks, Zach useful topic as always, I usually use direct connect for all vias(in 4+ layer PCB), and leave default relief enabled but use Solid Region on the areas that I want to be direct-connect but in 2-layer always use direct-connect and manually add thermal relief on needed pads.

[@robertbox5399]

We had big problems with high current traces and these reliefs. If there are several, each one acts like a progressive fuse until things go OC. The reliefs were only 0.5mm wide too!

[@TheDutchGuyOnYT]

I had more problems with a GND via like in 9:35, thermally bridging a big GND plane to a smd pad (solder problems), than with smd pads without thermal reliefs. (9:00) Especially with external assembly and with a good reflow oven + adequate thermal profile (time vs temp), never saw tombstoning. Smallest used 0402.

[@vipinckty1]

Hi Zac, can you please do a video on PCB pad as heat sink..and how to do the calculation

[@Readytobeamup]

For very small ICs/sensors I've noticed that the connection and copper area symmetry is important around the IC. This keeps the IC from moving during soldering. My feeling is that heat is applied to the pads from traces as well as through the package. If the traces and copper varies too much the pads heat out of sync and the part can rotate or move out of alignment.

[@onlinethappad6504]

hi, this video is informative. can you please share any video or document's link for Automatic SMD Neck Down? It will help me a lot for routing BGA packages.

[@azizzkkk]

Thanks Zack, pretty useful info. What would you say in the case of when we need to have relatively high current at high frequencies. Would it be better to use thermal relief on say the drain source pads of a mosfet? Especially if we want to reuse the boards and solder new mosfets?

[@Zachariah-Peterson]

Interesting question, I have never seen data specifically comparing signal vias with/without thermal connections. I have seen data on thermal reliefs used on vias for SMD capacitors, and there is an impedance difference that impacts the PDN impedance. In high frequency, the copper spokes will definitely have some effect on the impedance along the current path when you get to higher frequencies because those spoke connections have some parasitic content. Field solver will be required to determine the full effects.

[@melvinegberts2347]

direct connect is almost never really necessary. Thermal reliefs can actually conduct a pretty decent amount of current and the voltage loss over such a distance is negligible.

[@jimjjewett]

Is it fair to say that thermal relief is harmless on pins for unused options and on strapping pins (because they don't carry much current) but mostly unneeded for chips with more than a few pins per side and reflow soldering? (Or are cold joints a problem even without tombstoning?) For that matter, why is thermal relief even needed with reflow soldering -- does it support a shorter oven cycle, or something?

[@Zachariah-Peterson]

Cold joints can still be a problem even without tombstoning. When we did the podcast episode with Chrys Shea she mentioned that it can sometimes predictably occur on pads that are following the reflow direction when the pads are attached to a very large copper pour. This is because the copper can affect the cooling rate when leaving the oven, and if one side cools down too fast then you have the risk of shifting or tombstoning.

[@jimjjewett]

Partly my screen, but it was amusing to hear "Now I'm inside of Altium Designer" as the screen went dark...

[@hamode_]

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