Why Full-Rate CDR?

[@breezerlxd]

Hi, CC, Thanks for keeping posting new videos! I have a questions. at time 12.14 when you talked about the duty-cycle impact, I didn't fully understand why you said full-rate clock have accurate 50% duty cycle while in the half rate case the duty cycle can cause problem. Could you elaborate a bit on that? Thanks!

[@abhiruplahiri1]

I guess the point is duty cycle in FR sampling can eventually be sensed as an error and corrected for by the loop. Such impairment worsens the ber even in FR, but in HR the duty cycle error on half rate clocks may not even be sensed (eg A goes to left, B to right but T is aligned) leading to higher uncorrected error and thus higher ber. I let CC comment more and enlighten us.

[@circuitimage]

Hi Xiaodong, Thank you so much for the good questions. Also, thanks for the Abhirup's very good feedback, which aligns with what I tried to say. The duty-cycle distortion (DCD) may have a BER impact on all CDR no matter which topology or clock rate; therefore, we must do the duty-cycle correction (DCC) in another loop. The FR sampling's data & transition sample usually has a better DCC than the HR; therefore, the DCD of the FR is usually less. But adding a good design of DCC in the HR still can minimize the DCD as much as possible.

[@circuitimage]

Hi Abhirup, thanks for your very good feedback, which aligns with what I tried to say. :)

[@abhiruplahiri1]

@@circuitimage many thanks CC. Always looking forward to your interesting videos.