Why is pMOS is good to pass logic 1 and nMOS is good to pass logic 0? | VLSI by Engineering Funda

[@EngineeringFunda]

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[@싱하형-v4g]

I'm Korean I had difficulty in studying dikson's circuit because I can't understand pass transitor but thanks to you I wholly can understand Dikson's circuit Thank you

[@EngineeringFunda]

Your welcome dear

[@정성하-u3x]

@@EngineeringFunda I have some questions. Normally, Nmos's gate voltage used to input voltage, In this description, Why drain use as input? and I know Pmos's current flow from source to drain because majority carries as hole flow from source to drain. But Pmos'drain is used as Pmos's input Why drain use as input?

[@vinayakmishra4510]

Got a lot of conceptual clarity as to why exactly the PMOS are on top and The NMOS are at the bottom in the CMOS circuits, thanks a lot sir, the conceptual clarity makes sure that we are learning for knowledge and not just marks, thanks again

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[@ranjithkumar-vh7ev]

Mosfet is an symmetric device it will conduct if we replaced the source and drain terminals i think it should be on video too when explaining input and output

[@adyashananda7795]

Sir in p mos input in source but you take it as drain ??

[@ajaymalolan1497]

S and D are identical

[@ashokreddysajjala]

It looks like hence proved Sir. but can you tell me that the gate voltage for PMOS to be negative ie, -5v is logic 0 and 0v will be logic 1, such that here we are considering Vgs for NMOS which will be positive value and for PMOS Vgs will be negative so we are taking it as Vsg to consider positive voltage. Is it correct sir

[@mhdridwan45]

Thank you mr.,it make clear

[@EngineeringFunda]

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[@mansisharma2023]

best video, thankyou sir

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[@mansisharma2023]

@@EngineeringFunda we all (students) really appreciate your teaching style sir 👍🏻🙌👑

[@abdxlive]

sir please make a video on ptl d,t-ff,masterslave ff

[@EngineeringFunda]

T flip flop and masterslave flip flop is already covered in digital Electronics

[@nancharaiahpenumudi2184]

Nyc sir, if PMOS bellow the threshold means it will turn on. Example if input - 5V,threshold is - 2V PMOS is turn on only. Pls check time 9.10min in vedio sir

[@adithyam3202]

for nmos and pmos , why do you pick the input side as drain and output side as source?

[@kirani.201]

Nice explaination sir

[@EngineeringFunda]

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[@mohammadanowarhossain8699]

Thanks. It would have been brtter if you had discussed how pmos passes logic 1 at initial condition when output is zero.

[@EngineeringFunda]

It would be same as explained here

[@jiaxingchen1406]

can i ask why you use source of nmos as output? I though only drain can be used as output, and S is input

[@vipulupadhyay9669]

very good explanation sir

[@EngineeringFunda]

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[@rohanyadala9096]

Nice..

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[@vesangisaichaitanya7447]

You are the best sir

[@EngineeringFunda]

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[@PoojaKumari-jr1jh]

nice explanation👍

[@EngineeringFunda]

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[@pam_xoxo5184]

I have a doubt regarding this. In previous lecture, you told that in pMos, the current will flow from S to D. But, for proving here, you have taken D to S for pMos. Why is that so? I would be honoured to get a reply. And Thank you sir Your videos are really helpful.

[@solankibhavik5073]

Hii sir please put videos on equation of both

[@alexandersolon6548]

why did we assume tha Vs is equal to VDD-Vth ?

[@ishankundu906]

Vth is the threshold condition. For nmos if Vgs> Vth then it is on. Now when Vs > Vdd-Vth then Vgs = [ Vdd - (Vdd-Vth) ] < Vth. Hence Vgs< Vth and the nmos is below the threshold condition

[@RahulDas-sy6du]

Thank you 💕☺️

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[@vijithavj2080]

Thanku

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[@javiergomez8286]

What is Vtn?

[@CuongNguyen-id1ob]

Sorry I misunderstand when a nMOS's Gate is applied VDD, but no any other terminals are connected to GND (Drain is connected to VDD and Source is output, as in the first example), how could the nMOS figure out that the gate voltage is VDD (I mean there is no voltage reference for the nMOS)?

[@PredatorF-25]

Nmos needn't figure out what is gate voltage, it only needs gate-to-source voltage Vgs to operate. Vdd is generally used for logic 1.

[@vizviz72405]

Gate voltage is we are providing vdd

[@geethasowjanyabhrugumalla513]

How will the transistor turns off if the output voltage increases beyond vdd-vtn

[@vbag42]

it will turn off because it will no longer satisfy Vgs > Vtn so the channel will not be formed.

[@shuvodev3708]

❤

[@EngineeringFunda]

Your Appreciations, care and share matters a lot to me. #EnginneringLove. All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us. Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏

[@싱하형-v4g]

Can you tell me about my question please

[@proud_indian0161]

sir apko padhana nhi aata, you have a lot of knowledge but apke baate samaj nhi aati sorry