Why SerDes Design Challenges from Impairments?

2023 IEEE Solid-State Circuits Society (SSCS) talk at Atlanta, GA of Region 3 (Southeastern USA)
Topic- SerDes Design Challenges from Impairments at Georgia Institute of Technology (GT), Georgia, USA
Abstract- Over the past three decades, the demand of communication makes different kinds of standards evolute exponentially in speed. Along with the higher and higher wireline data rates, more impairments in the SerDes system and circuitry may results the link design challenges in an evolution. For example, the impairments, such as an inter-symbol interference, ISI (due to frequency dependent attenuation), crosstalk, reflection, noise, jitter, linearity, device mismatch, capacitive or inductive parasitic, power/ground integrity, etc., could not be a big concern at old generation SerDes, but could be an issue at a high-speed SerDes system and requires a careful design/verification to mitigate the impairments.
This presentation will begin with providing an introduction of a wireline serial link, including a few impairments. Then move forward with a few circuit design techniques to mitigate those impairments. The corresponding SerDes system and circuit design techniques would be explored during the iterations between those impairments and rearchitecting process. A further Q&A discussion will be performed in the end of this presentation.
Biography- Chung-Chun (CC) Chen
has been with Silicon Creations since 2011 and is a principal circuit architect for SerDes IO interface. Currently, CC leads SerDes team as a Director of Analog/Mixed-Signal Design at Silicon Creations in Atlanta, Georgia. Before joining Silicon Creations, he was a research staff member at Samsung Electro-Mechanics design center in Atlanta, Georgia, and he was a principal engineer at TSMC in Hsinchu, Taiwan, where he worked on clocking architecture design and related customer support.
Chung-Chun (CC) Chen (S’02-M’09-SM’17) was born in Taipei, Taiwan, in 1979. He received the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2004 and 2009, respectively. His current research interests focus on circuit designs in clocking and other SerDes building blocks for high-speed communication systems. He has published over 15 papers in peer-reviewed conferences and journals. He is a Senior Member of the IEEE and served as a reviewer of JSSC and T-MTT.

[@bobbylu3490]

Finally able to catch up the video. Thanks CC for the high quality materials.

[@circuitimage]

Glad you like them!😊

[@abhiruplahiri1]

Congrats for the SSCS video, CC. Its a very nice summary for serdes challenges in less than an hour.

[@circuitimage]

Glad you liked it!

[@madhooz]

as like always, very informative video on SERDES fundamentals at surface level. Thanks a lot for your efforts and looking forward for more videos on SERDES. 🙏🙏

[@circuitimage]

Hi Madhooz, nice to meet you and thanks for the nice words. I'm glad that helps and will keep my efforts helping everyone. 😊

[@srinivaskalwad]

Awesome Can you please make videos on high speed serdes serial videos or kind of basics

[@circuitimage]

Hi Srinivas, thank you so much for the suggestions. I'll do it. :)