X-propagation in SOC design flow | Do you Love your X !!

[@FPGASystems]

Very very good! I would say - excellent!

[@KarthikVippala]

Thank you! Sooooooo much 😃🙏

[@shivakumarpujuri7196]

The content you presented the way is awesome. Keep doing it 👍

[@KarthikVippala]

Thanks a ton

[@manojyenimi5058]

Informative video. Keep posting!.

[@KarthikVippala]

Thanks boi🙏

[@hemareddy793]

Nice info thanks 👍🙂

[@kvssumakar2182]

Thanks

[@rydamian]

This x-trap assertion should be: assert (^cond !== 1'bx) In your assertion: assert (^cond === 1'bx) error will be reported when there is no X value in cond. This assertion should raise an error when there is an X value in cond.

[@kvssumakar2182]

Why is the conditional operator modeled the way you have illustrated? Why is it different from normal if else ?

[@kvssumakar2182]

Why is the conditional operator modeled the way you have illustrated? Why is it different from normal if else ?

[@nikilkumar1917]

Any idea why we tell Netlist simulation (GLS) X pessimism?