Xilinx Vivado to Design NOT, NAND, NOR Gates.

This video demonstrates the use of Xilinx Vivado to design digital circuits using Verilog HDL.

[@kandagaddalavenkatakiransu5715]

his way of explaining is awesome ! the way he say's what to do step by step is so nice helps u learn in no time, one of the most under rated video 😤😤😤😤

[@dr.hariprasadnaikbhattu]

Thanks. But you wrote under rated. But don't mind

[@ylakshmichandra9181]

I am getting this error in vivado software "ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors."

[@dr.hariprasadnaikbhattu]

Hi, the option is to reluanch the simulation

[@edification_4all]

good initiative sir

[@dr.hariprasadnaikbhattu]

Thankyou

[@dhanushbenbenjohndavid9931]

how i generate verilog code using bloks like and,or gates etc..

[@dr.hariprasadnaikbhattu]

Hi, what I have shown is writing verilog HDL code for any design then convert it to block level

[@hassambinhassan4446]

sir what is the 11th video in this playlist? mistakenly added?

[@dr.hariprasadnaikbhattu]

Hi, it is others video which I have saved.

[@HimanshuKumar-rc9oq]

Not able to install vivado it install upto some initial stages then starts from 0 showing repeated download error how to install

[@dr.hariprasadnaikbhattu]

Download the copy of Vivado by registering. It works

[@HimanshuKumar-rc9oq]

I have tried not working share entire process

[@HimanshuKumar-rc9oq]

One or more files failed to download

[@manendra-uh2gz]

sir my output is stuck at z dont care condition, i dont know why

[@dr.hariprasadnaikbhattu]

May be any of the line is floating. Check once

[@manendra-uh2gz]

issue solved thanks@@dr.hariprasadnaikbhattu

[@animal.lover3463]

Tq sir

[@dr.hariprasadnaikbhattu]

👍

[@subhajitmahanta6974]

more videos

[@dr.hariprasadnaikbhattu]

Hi, I did most of the videos which are essential