This video demonstrates the use of Xilinx Vivado to design digital circuits using Verilog HDL.
Пікірлер: 21
@kandagaddalavenkatakiransu57157 ай бұрын
his way of explaining is awesome ! the way he say's what to do step by step is so nice helps u learn in no time, one of the most under rated video 😤😤😤😤
@dr.hariprasadnaikbhattu7 ай бұрын
Thanks. But you wrote under rated. But don't mind
@ylakshmichandra91816 ай бұрын
I am getting this error in vivado software "ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors."
@dr.hariprasadnaikbhattu6 ай бұрын
Hi, the option is to reluanch the simulation
@edification_4all Жыл бұрын
good initiative sir
@dr.hariprasadnaikbhattu Жыл бұрын
Thankyou
@dhanushbenbenjohndavid99315 ай бұрын
how i generate verilog code using bloks like and,or gates etc..
@dr.hariprasadnaikbhattu5 ай бұрын
Hi, what I have shown is writing verilog HDL code for any design then convert it to block level
@hassambinhassan44463 ай бұрын
sir what is the 11th video in this playlist? mistakenly added?
@dr.hariprasadnaikbhattu2 ай бұрын
Hi, it is others video which I have saved.
@HimanshuKumar-rc9oq4 ай бұрын
Not able to install vivado it install upto some initial stages then starts from 0 showing repeated download error how to install
@dr.hariprasadnaikbhattu4 ай бұрын
Download the copy of Vivado by registering. It works
@HimanshuKumar-rc9oq4 ай бұрын
I have tried not working share entire process
@HimanshuKumar-rc9oq4 ай бұрын
One or more files failed to download
@manendra-uh2gz10 ай бұрын
sir my output is stuck at z dont care condition, i dont know why