CADENCE GUARD RING

[@sonutiru8670]

hello sir, can you please tell me how can I display the layer names such as vdd, vss , gnd and so on. For some reason these names are not visible in my device

[@dr.hariprasadnaikbhattu]

Try this video kzbin.info/www/bejne/i5Wvgpuvis11jbs

[@vemayaswanth2506]

Hello sir, can you please do a video for 7T SRAM IC design

[@dr.hariprasadnaikbhattu]

Hi, I am working on it. But may take time

[@BrindhaThanjavur]

Sir I have tried by connecting pmos as integrated and nmos as detached. But the stamp error occurs. Pls give a solution.

[@dr.hariprasadnaikbhattu]

Is it during DRC or over all stamp error

[@BrindhaThanjavur]

@@dr.hariprasadnaikbhattu sir how to find its overall stamp error? Once after drawing layout, and checking for DRC I saw psubstrate stamp error _connect and substrate stamp error_mult. As you suggested I tried by detaching both pmos and nmos components, nmos alone. I tried for all combinations. I don't know how the error occurs?

[@dr.hariprasadnaikbhattu]

@@BrindhaThanjavur Hi it may be dimensions of nwell is less

[@BrindhaThanjavur]

@@dr.hariprasadnaikbhattu sir how to rectify? I couldn't clear these 2 errors only.

[@BrindhaThanjavur]

I thought of doing post layout. But these 2 error remains.

[@BrindhaThanjavur]

Sir while drawing layouts i am getting psubstrate stamp error mult. What does this error denote sir? Pls help me.I am in the verge of my reserch work completion. Kindly give your contact sir.

[@dr.hariprasadnaikbhattu]

Hi, in layout you might have only source, gate and drain. Substrate may be missing. it could be the reason

[@BrindhaThanjavur]

In 45nm usually I integrate both bulk and source sir. Because of that error I tried by detaching also.

[@BrindhaThanjavur]

If we opt detach option, while making connections should we have to attach manually those bulk and substrate? Because the path itself is showing to connect sir. Again if I do, I am getting same errors.

[@techabyt986]

Sir i need to contact you about the designing of fir filter using Domino logic in cadence

[@dr.hariprasadnaikbhattu]

Hi, what is the need of contact Can simulate the circuit based on reference videos

[@techabyt986]

Plz provide the reference videos sir I didn't find out

[@clintrobby5615]

Sir how to get cadence viruso..cracked version available?

[@dr.hariprasadnaikbhattu]

Hi, first it is not a free software. It is commercial. For crack check the website getintopc

[@aryap4710]

how to install it on mac ?

[@dr.hariprasadnaikbhattu]

Hi, it is commercial and can be installed on Linux system only

[@aryap4710]

so using VM how can I do sir? @@dr.hariprasadnaikbhattu

[@Marshal-y2y]

Please do it for alu in cadence please

[@dr.hariprasadnaikbhattu]

Hi, it takes time for large designs

[@dr.hariprasadnaikbhattu]

Takes time for large designs

[@LokeshK-y4q]

sir i need to contact you for designing 2x2 microstrip patch array antenna pls your contact sir

[@dr.hariprasadnaikbhattu]

Hi, I am not working on antennas now