ElectroTuts

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@suryakumar-en9tc 2 ай бұрын

How do we constrain or calculate setup/hold if data and clock are moving in opposite direction?

@sanamkala8795 3 ай бұрын

As per the diagram if resolution time is more the flop will be more in metastable state but as per the equation if resolution time is more the flop will come out of meta stability more quickly. These two statements contradicting each other. Please clarify this doubt.

@divyamsatle6673 7 ай бұрын

All I would say is this man can become brand ambassador of Sprite, siddhi baat no bakwas.

@juanruiz2603 8 ай бұрын

Thank you for this video! Very clear and straight to the point

@AbhishekVerma-rw2ks 9 ай бұрын

Tc should be time period of the receiving clock, not launch clock

@MedhanshMamidi Жыл бұрын

00:00 Metastability in Sequential Circuits 00:58 Understanding the effect of changing input D during aperture time 01:46 Metastability is the process of a flip-flop settling into a stable state. 02:37 Metastable state is unstable due to disturbances 03:23 Metastability and its causes 04:13 Asynchronous inputs can cause metastable state 04:58 Metastability in flip-flops can cause unpredictable data output. 05:45 Metastability can cause system failure

@ianespinosa7380 Жыл бұрын

Excellent explanation. I understand now.

@lokendrasinghlodhi718 Жыл бұрын

Thank You bro! I faced one question in Nvidia Placement test : FIFO depth if writing rate 45 beats/50 clock and read rate 12beats/20 clock?? when Burst size is not mentioned than how we will be able to find FIFO Depth?

@vivekkandhagatla3096 Жыл бұрын

You need to take the effective beats/clock for beats calc and Fifo depth = (effective beats/clock for write - effective beats/clock for read )* Burst size -> Burst size assume a number and round off the fifo depth to the nearest integer.

@ayushagarwal69 Жыл бұрын

which college did this exam happen in ?

@ayushagarwal69 Жыл бұрын

@@vivekkandhagatla3096 0.9-0.6 = 0.3 beats per clock loss , but I dont know the burst rate , so 3 should have been answer in that exam maybe ?

@lavanyakumanji524 Жыл бұрын

Very good explanation

@lavanyakumanji524 Жыл бұрын

You need to zoom in or write big I'm sorry unable to see

@digambarbhole9467 Жыл бұрын

Although a synchronizer avoids metastability, it can corrupt the data by settling it into incorrect state. How do we correct it?

@anupalike1226 Жыл бұрын

Hi can you please upload video for clock gating checks , it will helpful for us

@mohamed-abuhashem Жыл бұрын

💖💖

@arun1122l Жыл бұрын

Hi, what are the T0 and Tau parameter of the flop, how can we characterize these value in flop ? Thanks.

@billchan8682 2 жыл бұрын

Thank you very much sir for the explaination! For the hold time part in 20:48, you mentioned hold time is -tpd(I1). But shouldn't we take the delay from CLK to inverter to T1 (say tpd(I0) ) into accout? And the hold time should be tpd(I0)-tpd(I1) ? Looking forward to your reply!

@kavsgame Жыл бұрын

c to q only comes into picture when flip flops are involved

@gkdresden 2 жыл бұрын

You can also charge and discharge the capacitor only across RB using the output pin 3 of the 555 timer. The advantage is, that you can save 1 resistor and you reach 50% duty cycle. And you can also separate the charge and discharge resistor path using 2 diodes and 1 potentiometer between output pin 3 and the capacitor to get every duty cycle at a certain frequency.

@lilslice1958 2 жыл бұрын

thanks so much subscribed!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

@shuvambiswas458 2 жыл бұрын

Can you suggest CDC book or any pdf

@veeryanbhatia538 2 жыл бұрын

helpful!

@michaelbradley7621 2 жыл бұрын

If you the drains are connected together, how can we say that, when A = high, the PMOS doesn’t have a drain current but the NMOS does have one. Wouldn’t the same current flow in the wire? Thanks for the video.

@mythathchr 2 жыл бұрын

Lets say there is no metastability issue, but the resolution is wrong, then synchronizers isnt the solution, is it ? how to deal with such a problem ?

@risheek4839 2 жыл бұрын

Hi bro can you do more videos on digital profile interview questions

@niharachakonda4067 2 жыл бұрын

Tq sir I'm searching this topic few days but no 1 can explain like u

@AbhishekSingh-up4rv 2 жыл бұрын

@pseudohawk1656 2 жыл бұрын

Thanks a lot

@robertwitt1276 2 жыл бұрын

seriously such an amazing explaination

@202ogananda6 2 жыл бұрын

Link please

@silicon_talks 2 жыл бұрын

how setup violation can be fixed by increasing the frequency,we need to reduce the frequency ,right?

@shreyithjamin7799 2 жыл бұрын

After installation when i run the program it displayed Unable to get Domain name in registry

@generalcontents5912 2 жыл бұрын

Could I get your PowerPoint file please

@amedirat 3 жыл бұрын

The author did not account for the worst case scenario when there is back to back burst as in 100 + 100 The depth should be 90*2 = 180

@lavanyapadala3119 3 жыл бұрын

Its not available from mentor graphics

@leozendo3500 3 жыл бұрын

The vicious music every once in a while is all that's keeping me focused 🤣

@debasishkar761 10 ай бұрын

😄😃

@zeyadf1644 3 жыл бұрын

I wish you were teaching me

@rohitgaykhe9883 3 жыл бұрын

explain once again the last HTC when inverter is added.

@alex0817ph 3 жыл бұрын

Thanks. Good help!

@shubhamnayak9369 3 жыл бұрын

Nice video

@harihara.t 3 жыл бұрын

Someone explain what the synchronizer circuit be in the first case where fa<fb?

@harihara.t 3 жыл бұрын

How did Pipelining have reduced STC?

@azharuddin7013 3 жыл бұрын

I understood the concept of synchronizers. However, my question is that if the metastability state can go either way i.e 1 or 0 then we haven't really captured the original d input. if D is 1 but it changes during setup or hold time and we get metastability state at Q and let's say it goes to 0 eventually then as you can see we have sent wrong value to second flipflop. So what do you do with this? Plz answer

@shubhamnayak9369 3 жыл бұрын

Same question

@fornax205 2 жыл бұрын

Metastable states cannot be eliminated with a synchronizer; the probability of failure P(failure) is always greater than zero. So what do we do with this? Communications protocols often use data encoding schemes that facilitate bit error detection (recognizing that a given bit has the wrong value), error correction, redundancy, etc., to reduce the statistical probability of erroneous data. But again: nothing is perfect; no system can completely eliminate these errors. The best we can hope to do is design a system that reduces the value of P(failure) to some practical and realistically-achievable small value (the closer to zero the better), and thereby ensure that the bit errors-which are unavoidable and inevitable-are extremely rare occurrences-e.g., on average, the system experiences no more than one bit error per ten years of continuous operation.

@salyiu3722 3 жыл бұрын

Hi there, I may be wrong about the TPD in the time 3:28. Should it be measured from the falling edge of the clock to the output signal becoming stable?

@jyh4820 3 жыл бұрын

Thank you

@zishanshaikh02 3 жыл бұрын

What is vdd???

@HardwareNinja 3 жыл бұрын

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@ujjawalagrawal5195 3 жыл бұрын

wonderful explaination e

@vlsikr 3 жыл бұрын

Nice. Setup-time Violation or Hold-Time Violation, which one is worse?

@HardwareNinja 3 жыл бұрын

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@endlurihareesh1797 3 жыл бұрын

Hi your videos are really good and helping me lot.Can u please make a video on FSM example for overlapping and non overlapping Interview based questions for critical cases.

@tariqueanwar4255 3 жыл бұрын

I think in the topology1: The output will be available after 2 clock pulses for the change at input side: 2X10ns = 20ns while in the topology 2: The output will be available after 3 clock pulses for the change at input side: 3X8ns = 24ns

@manojharshavardhan2385 3 жыл бұрын

Why can't we divide the comb logic delay as 3ns each then the T will be 7ns & Fmax is about 142.8Mhz which is better than 125Mhz. Also the output after 2 Clk Cycles will be at 14ns rather than 16ns. Can we consider this case??

@harihara.t 3 жыл бұрын

It was just an example that he took 4 and 2

@manojharshavardhan2385 3 жыл бұрын

Waiting for more great content in STA. Subscribed👍

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