Electronics Interview Questions: STA part 1

Are you preparing for placement interview in hardware profile? This video will guide you through the most commonly asked interview questions related to the static timing analysis which is the most commonly asked topic in interviews for digital profile.
Link to my videos on basics of Static Timing Analysis(STA) of Digital circuits:
Part 1: Combinational circuits:- • Static Timing Analysis...
Part 2: Sequential circuits:- • Static Timing Analysis...
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Thank You!

[@Deepakkumar-tq1xv]

Best ever explanation for STA. Keep posting such videos..

[@electroTuts]

Thanks for the support !!

[@gudipatiramu5984]

I really liked the Inverter Question. But, detail explanation would be much more helpful.

[@GaneshPatil-vj1qp]

Too good explanation on this topic so far i have seen anywhere👌👏best👍Thank you😊

[@HardwareNinja]

Hi Ganesh, check us out for engineering interview related questions. We'd love to hear your feedback! kzbin.info/door/7h3PROcX7Zgx00alQokJ-w

[@pavankumarreddy7888]

I dont think there will be any hold time violation for the clock diagram for the case of inverted clock given to the 2nd FF becz.. Anyways data will be held constant by the 1st FF while 2nd FF is sampling the data if the Set- up time constraint is met.

[@hm6936]

When adding Buffer time (skew) to setup time equation (time 7:00) i think it should be tcq+tpd+tsetup+tb

[@ANKITMAURYA-sj9dg]

same doubt regarding this

[@mayureshjoshi7494]

@@ANKITMAURYA-sj9dg T is the total time period of the clock path. If we are inserting a buffer of delay tb in the clock path, the total time of the clock path will be T+tb

[@007DARP]

I watched all your videos regarding Timing Analysis. In the second Video you did the analysis considering clock skew and in the third with buffer. Shouldn't the Static time analysis equation of both will be the same? Just like the Hold time Analysis. Because Clock Skew and Buffer both are adding the delay in the clock of the second Flipflop.

[@cburrito1000]

nice list of videos. very useful and understandable

[@tuongluongthanh2030]

thank you for your presentation !

[@shashikantsingh4993]

good work bro...it is really helpful

[@jiaabhiraaj9449]

Bahot badhiya content

[@kalyan157]

Heyy you are excellent.Thanks a lot.Please do more

[@electroTuts]

Thanks for your support Kalyan, will make more videos as soon as possible!

[@MichaelAaronBerger]

As everybody has stated, it should be tcq + tpd >= thold + tinv + T/2. since in his example, at -t/2 on rising edge is before the first flipflop even started.

[@HardwareNinja]

Hi Michael, check us out for engineering interview related questions. We'd love to hear your feedback! kzbin.info/door/7h3PROcX7Zgx00alQokJ-w

[@RandomHubbb]

the content is great, thank you. but i have an unrelated question : I like your handwriting and the pen you are using. What brand and type of pen is that? i keep looking at the stores and could not find a similar tipped pen so far :)

[@anirudhkashyap5393]

Could you explain the hold time constraints for the inverted clock case because I am getting it as tcq + tpd >= thold + tinv + T/2

[@rambalaji725]

Me too

[@rambalaji725]

Is it wrong in the video?

[@aashnajain6519]

Me too

[@rohitgaykhe9883]

me too

[@harshavardhanmittapalli5605]

Hi, why in the inverted clock case setup time check is with respect to same clock edge (after all it can be seen as a delayed clock with clock skew equal to inverter delay plus T/2).why not with respect to next clock edge??

[@electroTuts]

great question!! You can do in that way also, then you have to meet the setup constraint of the next clock edge and hold constraint of the same clock edge. Then, STC becomes tcq + tpd + tsetup = tinv + T/2 + thold Depending on the delays between the 2 flip flops, the case shown in the video or the case you have considered should be choosen. I hope that I answered your question!!

[@harshavardhanmittapalli5605]

Thanks for the reply @electroTuts. So it all depends upon the delay. But if we consider the case that was illustrated in the video then the output is available before the second clock cycle ( i mean before second edge occurs). We expect the output to be available after 2 clock cycles as we have 2 FF's. As it was the case in clock with out inverter.

[@electroTuts]

Exactly !!

[@harshavardhanmittapalli5605]

So in that case the data that was available at the input of second FF is overwritten.

[@manojharshavardhan2385]

So basically in this case we consider the hold analysis for current clock edge and the setup analysis for the next clock edge.

[@vlsikr]

Nice. Setup-time Violation or Hold-Time Violation, which one is worse?

[@HardwareNinja]

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[@rohitgaykhe9883]

explain once again the last HTC when inverter is added.

[@priyasahoo4280]

as I have studied hold violation doesn't depend on clock period but here in case of inverter we see it is depending on T. please clarify.

[@akshaygehi11]

I have the same question.

[@HardwareNinja]

Hi Priya, check us out for engineering interview related questions. We'd love to hear your feedback! kzbin.info/door/7h3PROcX7Zgx00alQokJ-w

[@bitopantalukdar9820]

The way you are holding the seems as if your index finger will break sir.....

[@maheshmahi2328]

Music is annoying and very weird