Electronics Interview Questions: FIFO Buffer Depth Calculation

FIFO depth calculation and basics of clock domain crossing is touched in this tutorial. This video provides a logical way to go through one of the most common hardware interview questions where you are provided with two different clock domain systems and you are required to transfer data between them.
The link for STATIC TIMING ANALYSIS related interview questions:
• Electronics Interview ...
Article on Metastability: electro-tuts.blogspot.com/2018...
Link to my videos on the basics of Static Timing Analysis(STA) of Digital circuits:
Part 1: Combinational circuits:- • Static Timing Analysis...
Part 2: Sequential circuits:- • Static Timing Analysis...
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Thank You!

[@arshiaj3751]

finest and clear explanation ever gone through!

[@ananthalavanya3143]

Simply super . explained in such a way even a beginner with out any knowledge can understand.

[@Paul_Lanka]

your explanation is really simple and sweet

[@jaslife87]

Thanks for the clear explanation!

[@knowledgeunlimited]

It's cool explanation, loved it!

[@rakcea]

the finest explanation :)

[@praveenmamidi8726]

Simple and Clear👍

[@sumukhabharadwajmohanrao853]

Much needed! Thanks for the video with great information :-)

[@mamathagollavilli9]

Explaination is really good... Plz share ur knowledge... With us...

[@Deepakkumar-tq1xv]

Your videos are really good for nice and clean concept building. I would love if u can make a video on 3rd method of synchronization that is hand shaking bw 2 clk domains

[@jairamgouda]

Great video. Please make a video on much complex problems related to FIFO design

[@narenkayarmar]

Now i figured it out !!!, Thanks :)

[@divyamsatle6673]

All I would say is this man can become brand ambassador of Sprite, siddhi baat no bakwas.

[@pavanbhandari1177]

very well explained

[@sharukhshaik7476]

Awesome explanation of fifo depth

[@electroTuts]

Thanks Sharukh!

[@ujjawalagrawal5195]

wonderful explaination e

[@hemchandjain2189]

please explain burst size briefly ,,,,,,,,,,,and thanks!..its really finest time taken video...ever seen.

[@prashantjain1180]

Very Clear Explanation................... One doubt is there that single bit is written or read in one clock period, then how you had taken whole in single period?

[@nitpl12]

Thank you 😊

[@kunliu5004]

Thanks for tutoring. It is really helpful. How long does it fill the FIFO, if the FIFO depth is 20 depth?

[@ravindrasuryavanshi6821]

Really mind blowing explanation

[@electroTuts]

Thanks for your support !!

[@sairambingi9937]

awesome

[@jyh4820]

Thank you

[@muhammadatif5480]

nice one

[@yprashant66py]

Bahut bhadiyan

[@veeryanbhatia538]

helpful!

[@sultanmurad2309]

Outstanding sir

[@electroTuts]

Thank you !!

[@ranjanparnami]

FIFO size = (fram size / TX freq) × (Tx freq - Rx freq) = (100/200MHz)× (180MHz) = 90

[@hariharakumar891]

Someone explain what the synchronizer circuit be in the first case where fa

[@vinayakkumthekar7752]

make such more videos

[@sunilkumarkp4508]

Super

[@maheswarreddy4394]

Can you explain the same example with 3 idle cycles while reading and 1 idle cycle while writing

[@anupalike1226]

Hi can you please upload video for clock gating checks , it will helpful for us

[@merrygo7189]

Nice video sir

[@electroTuts]

Thanks for your appreciation !! :)

[@anilkadiyala]

Is fifo required even in the case of fa < fb ? . I see some fifo depth caluclations on the net in this case. can someone explain ?

[@yasirpunathil7143]

No, we just need a synchroniser, since receiver unit is faster than transmitter, there won't be any data "lost in translation" if we synchronise properly

[@juntran_workbackupleppy7024]

Explaned nicely ..... but what exactly mean you want to describe for idle cycles? that can you elaborate here?

[@saiprasadszhayi]

It basically means that you have an idle cycle that does nothing after a consecutive write or read. In that case, you would have to multiply the calculated time period by the number of idle cycles mentioned. Say for example, if you insert 2 idle cycles after every read (Trd =3* (1/read clock f)).

[@alokmishra9522]

.

[@lizajoseph6368]

For the scenario 1 FA < FB, if FA = 60 MHz and FB = 100MHz how we will send data without FIFO? For the scenario 2 FA = FB and clocks are not in Phase how can we send data without FIFO?

[@ahmadalastal5303]

in scenario A, let us say that you are writing data to RAM, in this case your writing slower than reading, in other words read all data in RAM and wait for another data to be written in RAM, this doesn't need a FIFO, in scenario B if they are not in-phase either you lock their phases or synchronize both using flip flops or of course you can use FIFO, it is up to you (the designer) to decide based on the system that he/she is building

[@alokmishra9522]

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[@Paul_Lanka]

if fa>fb for single bit data crossing, what synchronizer is preferred...

[@electroTuts]

That will depend on the design, use-case, etc. The video gives an overview into the problems and how to mitigate it!

[@Paul_Lanka]

@@electroTuts ok Sure and Thanks for the replay. Also could you please kindly do more video's on CDC.

[@lokendrasinghlodhi718]

Thank You bro! I faced one question in Nvidia Placement test : FIFO depth if writing rate 45 beats/50 clock and read rate 12beats/20 clock?? when Burst size is not mentioned than how we will be able to find FIFO Depth?

[@vivekkandhagatla3096]

You need to take the effective beats/clock for beats calc and Fifo depth = (effective beats/clock for write - effective beats/clock for read )* Burst size -> Burst size assume a number and round off the fifo depth to the nearest integer.

[@ayushagarwal69]

which college did this exam happen in ?

[@ayushagarwal69]

@@vivekkandhagatla3096 0.9-0.6 = 0.3 beats per clock loss , but I dont know the burst rate , so 3 should have been answer in that exam maybe ?

[@amedirat]

The author did not account for the worst case scenario when there is back to back burst as in 100 + 100 The depth should be 90*2 = 180

[@pavanhegde1933]

Can we calculate depth of FIFO if we don't know burst size? I mean I want read to continuous. I didn't got u r infinite depth FIFO so clearly please clarify me

[@danieljimenez1989]

If data is continously being fed to the fifo from a faster clock to a slower clock, then no fifo will ever have enough depth. Every cycle of the read, you get more than one cicle on the write, so as time goes on the fifo gets more and more filled up. At some point, if the writing side never stop, it will get completely filled up, unless the fifo had infinite depth.

[@alokmishra9522]

.

[@sultanmurad2309]

Q1) draw a neat diagram of astable multivibrator using op amp explain it's work and hence derive an expression for its pulse How this pulse????Sir solve this problem Plzzz

[@electroTuts]

Will consider this when deciding a topic for future videos!

[@sultanmurad2309]

Sir I am started now 1 November coming on

[@mjitglv5876]

Thanks for the clear explanation!

[@electroTuts]

Glad it was helpful! :)