Electronics Interview Questions: STA part 2

Are you preparing for placement interview in hardware profile? This video will guide you through the most commonly asked interview questions related to the static timing analysis which is the most common topic asked in an interview for a digital profile. This video is in continuation with the part 1 of the same with its link below.
Electronics Interview questions Part 1: • Electronics Interview ...
Video on Metastability: • Metastability - Part 1...
Link to my videos on the basics of Static Timing Analysis(STA) of Digital circuits:
Part 1: Combinational circuits:- • Static Timing Analysis...
Part 2: Sequential circuits:- • Static Timing Analysis...
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Thank You!

[@electroTuts]

Check out my new blog at www.electro-tuts.blogspot.com !!

[@ramyam6782]

I do have a question to overcome set up violation we have to increase the time period which is nothing but reducing the frequency ...but how it will help by increasing the frequency beyond fmax ???

[@anandayr66]

Simplistic and down to earth approach, explained accurately to the point. Understanding timing analysis is a crucial part of design constraint. Thank you for providing solid insight on timing constraints and this is where I got best explained and neatly organized constructive details about this topic. I conclude my point by saying that you are doing devotional work and value-based service, so that keep sharing your knowledge and enlightening with your virtues. Truly inspiring. Thank you for your treasured time.

[@electroTuts]

+Ananda Y R thanks for your support!!

[@dnssabarish]

Awesome explanation! Pls continue making more videos on interview questions like this!

[@electroTuts]

Thanks Sai!! Will definitely make more videos soon!

[@manojharshavardhan2385]

Waiting for more great content in STA. Subscribed👍

[@manojj2234]

wow! just wow!! thanks for this video buddy :)

[@leonshen8093]

Very good explanation. But could you also talk about multi-cycle setup and hold? Can we also use multi-cycle constrain method if the setup and hold constrain in a single cycle is not met?

[@rahulrajkashyap5845]

explained wonderfully..thanks

[@veereshranjan3519]

Fantabulous all the 4 videos

[@tariqueanwar4255]

I think in the topology1: The output will be available after 2 clock pulses for the change at input side: 2X10ns = 20ns while in the topology 2: The output will be available after 3 clock pulses for the change at input side: 3X8ns = 24ns

[@anuragbagewadi]

Was very helpful... Heartly thank you 😊

[@msubash4053]

Thanks for your video bro

[@manojharshavardhan2385]

Great job 👍

[@suryakumar-en9tc]

How do we constrain or calculate setup/hold if data and clock are moving in opposite direction?

[@张良-k6x]

讲的很详细，非常感谢

[@manojharshavardhan2385]

Can you translate

[@harshitmakwana8917]

Great lecture. I have one doubt. Is there any way to retimed the circuit such that max operating frequency will increase without affecting latency??

[@electroTuts]

Hi Harshit, You can possibly design FlipFlops with better setup time and Hold time requirements to decrease the margin taken by them. You can reduce the delay of the combinational logic by tweeking with the transistor's parameters. So, there are possibilities to retime the circuit but they often comes at some cost(maybe area, maybe power) and the overall design issue is solved by considering the tradeoffs under which your specific design is acceptable. I hope this helps to give you a perspective !!!

[@sksameer208]

Fantastic!

[@sunshinekanika5797]

amazing video

[@silicon_talks]

how setup violation can be fixed by increasing the frequency,we need to reduce the frequency ,right?

[@vinodummeda3726]

can give elaborated reply on hold time violation if inverted clock is applied to capturing flipflop..u told in first video...but it is not at all understanding...please

[@naveenkumararva1892]

Nice

[@adigokhale90]

I came across one more question that what will do if setup time or hold time or both violation is present in fabricated chip. How will you make it work?

[@electroTuts]

Hi, Industries usually invest a large amount of time in verification and pre-silicon validation so that no bug in the design propagates to the actual silicon(fabricated chip). But still, if the violations are present in the chip, a usual method is to reduce the operating frequency of the chip (this technique fixes only setup time violation). Hold time violations can't be fixed because there is no frequency related term in the hold time equation(frequency is usually the only variable which can be tweaked after fabrication). So, the chip is designed and fabricated again. I hope this answers your question! :)

[@kalyanianu3809]

Hi thank you for the video, it is very helpful but ad 7:07 isn't it 8ns+6ns=14ns instead of 16ns? Please reply

[@electroTuts]

Hi Kalyani, Sorry for the late reply. No, it must be 16ns. It is found that the circuit has a maximum frequency of 125MHz. Input of that frequency is given as clock(Clk). At first Clk pulse (At time = 8ns), input is received by the second FlipFlop and then after second Clk pulse(At time = 1ns), Input reaches third FlipFlop. I hope it helps !!

[@orugantimanideep2209]

No, if you calculate T for both the clock cycles, you will get 8,6ns. So, max. allowed frequency must be the lesser one. So, it must be from 8ns. Now, you fixed your clock to 8ns. So, even you have your input ready by 14th ns, it will be read only at 16th ns since the second clock edge comes at 16th ns. Please ask if you don't understand 😁

[@manojharshavardhan2385]

Why can't we divide the comb delay as 3ns each then T will be 7ns with Fmax about 142.8Mhz which is better than than 125Mhz and the output after 2 cc with be at 14ns. Why can't we consider this case.

[@orugantimanideep2209]

@@manojharshavardhan2385 Of course, you can do this if delays of both the gates are equal. Here, he assumed the combinational delay to be from two gates with 4, 2 ns.

[@hariharakumar891]

How did Pipelining have reduced STC?

[@rajaposupo8376]

Good explanation. But use Dark pen....

[@dnssabarish]

Waiting for the latest videos!

[@electroTuts]

Unable to get time, will make videos as soon as possible :)

[@manojharshavardhan2385]

Why can't we divide the comb logic delay as 3ns each then the T will be 7ns & Fmax is about 142.8Mhz which is better than 125Mhz. Also the output after 2 Clk Cycles will be at 14ns rather than 16ns. Can we consider this case??

[@hariharakumar891]

It was just an example that he took 4 and 2