What is Reverse Case Statement in Verilog? Case(1'b1)

Case (1'b1) is called reverse case statement ,used typically for synthesizing a one-hot fsm, because synth tools infer comparatively less logic than the other way of writing a case statement .
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🔗 Resources :
- www.sunburst-design.com/papers...
- Darshan Alagud
🔥 Thanks for watching , Have any doubts comment down , happy to help you. Please Do Subscribe .

[@omersarcam3070]

Your sense of humor and explanation are very good.

[@shrutitajne]

Accidentally stumbled on this channel, the title of this video intrigued me. I enojoyed the concept and explanation, it was new to me but more than that, absolutely loved the animations!!

[@KarthikVippala]

🫡Thank you

[@antonymathew]

thanks a lot brother.. never seen such a great clarity in explanation for digital design.

[@golinagasandesh4464]

Wow!! Great channel for exploring the depths of Verilog

[@KarthikVippala]

Thank you, brother 🙏

[@tientranmanh798]

You should create a video about statemachine using one hot coding. It will bring more value when we use case(1'b1) and enumaration. I love to see your video :D

[@KarthikVippala]

Yes it would more value, Sure will do it

[@mpraveen4937]

Thank you .. very much

[@KarthikVippala]

Your welcome🙏

[@abhiverma812]

Don't use parallel case pragma. Instead use unique decision modifier in front of the case statement. This will ensure that state index is one hot coded. It will give a RT warning in simulation too. Synthesis tool will understand it too.

[@KarthikVippala]

Yup 😊👍