#28 casex vs casez in verilog | Explained with verilog code

casex vs casez in verilog | Explained with verilog code
In this verilog tutorial video casex and casez statement uses has been explained in simple and detailed way. Difference between casex and casez has been covered in this verilog tutorial.
Lesson-1 Why verilog is a popular HDL • #1 Why verilog is a po...
Lesson-2 Operators in verilog(part-1) • #2 Operators in Veril...
Lesson-2 Operators in verilog(part-2) • Operators in Verilog (...
Lesson-2 Operators in verilog(part-3) • Operators in Verilog( ...
Lesson-3 Syntax in verilog • #3 Syntax in Verilog ...
Lesson-4 Data types in verilog • #4 Data types in veril...
Lesson-5 Vector and Array in verilog • #5 {Error:check descri...
Lesson-6 Modules and port in verilog • #6 Module and port de...
Lesson-7 Gate level modelling in verilog • #7 Gate level modelin...
Lesson-8 Dataflow Modeling in verilog • #8 Data flow modeling...
Lesson-9 Behavioral Modeling in verilog • #9 Behavioral modelli...
Lesson-10 Structural Modeling in verilog • #10 How to write veri...
Lesson-11 always block in verilog • #11 always block in V...
Lesson-12 always block for combinational logic • #12 always block for c...
Lesson-13 sequential logic in design • #13{Mistake:check desc...
Lesson-14 always block for sequential logic • #14 always block for s...
Lesson-15 Difference between latch and flip flop • #15 Difference betwee...
Lesson-16 Synchronous and Asynchronous RESET • #16(MISTAKE-Read Descr...
Lesson-17 Delays in verilog • #17 Delays in verilog ...
Lesson-18 Timing control in verilog • #18 Timing control in ...
Lesson-19 Blocking and Nonblocking assignment • #19 Blocking vs Non Bl...
Lesson-20 inter and intra assignment delay in verilog • #20 Inter and intra as...
Lesson-21 Why delays are not synthesizable • #21 Why delays are not...
Lesson-22 TESTBENCH writing in verilog • #22 How to write TESTB...
Lesson-23 Multiple always block in verilog • #23 Multiple ALWAYS bl...
Lesson-24 INITIAL block in verilog • #24 INITIAL block in v...
Lesson-25 Difference between INITIAL and ALWAYS block in verilog • #25 Difference between...
Lesson-26 if else in verilog • #26 if-else in verilog...
Lesson-27 CASE statement in verilog • #27 "case" statement i...
Lesson-28 CASEX and CASEZ in verilog • #28 casex vs casez in ...
Lesson-29 FOR loop in verilog • #29 "for" loop in veri...
Lesson-30 WHILE loop in verilog • #30 "while" loop in ve...
Lesson-31 FOREVER in verilog • #31 " forever " in ver...
Lesson-32 REPEAT in verilog • #32 " repeat " in veri...
Lesson-33 GENERATE in verilog • #33 "generate" in veri...
Lesson-34 FORK-JOIN in verilog • #34 " fork and join " ...
Lesson-35 named block in verilog • #35 Named block in ver...
Lesson-36 TASK in verilog • #36 (MISTAKE-Read Desc...
Lesson-37 FUNCTION in verilog • #37 (MISTAKE-Read Desc...
Lesson-38 WIRE vs REG in verilog • #38 Wire vs Reg | when...
Lesson-39 FSM-MEALY state machine in verilog • #39 Finite state machi...
Lesson-40 FSM- MOORE state machine in verilog • #40 Finite state machi...
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[@jitubaba5450]

Thank you for sharing. Always love learning your verilog tutorial.

[@circuitsanalytica4348]

Yes Jitu, really nice videos.....

[@ujwalkumarbcj9362]

Hi sir, at 10:25 you took case expression as 2'bxx (i.e a = 2'bxx) and we have case item as 2'b1x, you said that it will match the case statement, so the b became 1. When I tried from my side for the below code I am getting Matched for case items: 00 ,01,0x,0z,x0,x1,xz,xx,z0,z1,zx,zz Not Matched for case items: 10,11,1x,1z module tb; reg [0:0] a=2'bxx,b; initial begin casex(a) 2'b1x: $display("Matched"); default: $display("Not Matched"); endcase end endmodule my doubt is as we are giving case expression as 2'bxx , then it should match the case items (10,11,1x,1z also). But here it is not happening. Could you please give me clarification regarding this?

[@ujwalkumarbcj9362]

It’s now resolved sir, I did a mistake while declaring varibales it should be reg [1:0] a,b; Now for all the values i am getting b = 1 . Thank you for the explanation sir

[@rajsambhav665]

Great explanation. what if there are multiple ones in the input. e.g for an input encoding = 4'b011x which next state will be executed ?

[@ComponentByte]

Thank you. It is decided by simulator. 011x equals 0110 and 0111 so next can be 8,9,10.... so 1xxx is enough for 8 to 15

[@teketinikhilkumar7905]

sir In 1st example , given encoding =10xz it can be 101z right so in the third case(xx1x = 101z) so cant we write next state=1

[@ComponentByte]

It's decided by simulator. If input=10xz then simulator will first check 1st case : if it matches then it will give 1st case output, if no matches it will go to next state. Thus 10xz matches 1st case 1xxx so simulator stops there and gives corresponding output .

[@teketinikhilkumar7905]

@@ComponentByte thank you sir

[@muhammedsayedm8174]

In case of casex why xz=zx compilation is not coming

[@amaryadav-mb5sx]

Sir in case statement eg. Case( s1, s2) =case(s1, s2) are same ????

[@ComponentByte]

No.They are different. 'case' is case sensitive(If I have written somewhere then it's just an example and definitely it's not in program)

[@darageorgieva3203]

Imagine we are in casex and we have 3'b1xz as in the first slide of the presentation. Aren't the possible options: 3'b1xz, 3'b1zx, 3'b1zz, 3'b1xx, 3'b100, 3'b101, 3'b110 and 3'b111?

[@ComponentByte]

Yes, you are absolutely correct.

[@digambarbhole9467]

sir, what is the physical significance of caseX and caseZ statements? can you please clear it?

[@ComponentByte]

This is a tool dependent construct means it generates a piece of different hardware as described in a synthesis tool. It generates mostly MUX based hardware.

[@digambarbhole9467]

Ok thank you sir

[@prasannan2084]

In casex 2'bzz also possible right?

[@ComponentByte]

Yes, possible. 2'bzz , here zz is considered as 2 don't care. zz can be 00,01,10,11

[@SebJames55]

Thank you 😁

[@ComponentByte]

Happy learning.

[@circuitsanalytica4348]

Yes, really nice video, isn't it....

[@vishalmoladiya2735]

Nice explanation: But in the last example When a=xx then I think b=1 and c=1 or 0 in c value I confused because in verilog casex has value of x is 0 1 x and z! But in simulation x take only value of 0 and 1 ? Is this r8?

[@ComponentByte]

In casex X value can be 0 or 1 and Z value can be 0 or 1. X is 0,1,X Z is 0,1,Z

[@hulkmania9487]

@@ComponentByte so why in starting u have taken 2'b1Z (first example in casex)

[@ComponentByte]

You mean why 2'b1X = 2'b1Z ? If it's your query then in casex all X and Z can be considered as don't care so X can be 0,1,X,Z So 2'b1x = 2'b10,11,1x,1z Don't care means your output doesn't depend on those input bits. If it's not your query then please let me know.

[@hulkmania9487]

@@ComponentByte cleared 👌

[@abhilash29130]

at 10:24 , Sir u have said XX can be 1X, 0X, X0. So according to it when a=0X then b should be equal to 1 instead of 0 ?

[@ComponentByte]

For casex When a=0X b=0 When a=XX b=1

[@abhilash29130]

As u have said in 1st example of casex, 2'b1X = 2'b10, 2'b11, 2'b1X, 2'b1Z and 1 should be fix and X should change So, why in testbench code in casex 2'b1X as, a=XX is taken? Will here 1 is not fixed ? [I mean how XX is inside casex ?] Please clarify..

[@ComponentByte]

Xx can be 1x,0x,x1,x0,00,01,10,11 and few others for casex only and not case. So when a=xx it results b=1 as here xx can be 1x also

[@abhilash29130]

Sir then why, When a=0X b=0 It should be b=1 right ? I am bit confused in this!! Please clarify..

[@ComponentByte]

When a=0X Here second bit is fixed that is 0 and can't be changed and 1st bit is X so can be 0,1,Z So 0x can't be 1x For 1X , we get b=1 for 10,11,1x,1z and for rest we get 0

[@sarathchandra5305]

can you tell me where do we use the casez in real time?

[@ComponentByte]

It can be used to design multiplexer if resources are available. Casez is used for testing the RTL code. During verification process code coverage is done to test every lines of code to check whether every lines of code is executed with valid input or not. In casez Z means if input is souriously 1 or 0 then the output should not be propagated and must be filtered out. Hope it helps.

[@shivammahato163]

what is casee instl ?

[@ComponentByte]

casee is module name (in module casee() )and inst1 is the name of module instatitaion.it can be any name you wish to write.

[@shivammahato163]

@@ComponentByte thank you