DVD - Lecture 3b: HDL Compilation

[@rogerfederer6456]

why do you say synthesis is iterative? do we have to run it multipletimes on the same file?

[@AdiTeman]

Hi, Actually, the entire physical design flow is iterative. It is actually iterative in more than one way. The first way of looking at it is that you run each of the steps many times with different parameters and each time you look at the results, analyze them, modify parameters and/or the design and re-run. Another level of iteration is the algorithms themselves, which usually have some optimization flows within that incrementally improve the result until the constraints are met, no improvements are made or a certain amount of time/effort has elapsed. I hope that answers your question.

[@SudhirPatel46]

Hi @AdiTeman I've been watching your videos for quite sometime and I really enjoy watching them. I've learned a lot. I aspire to be a Design Engineer. I would really be greatful if you make a video on roadmap for being a Digital Design Engineer. Also I've been using SystemC for my work and I often get confused about should I go for Verilog or systemC?? Please I would like to hear your thoughts on this.

[@AdiTeman]

Hi, Sorry for my very belated response. Been busy lately (...more than the usual). Thanks for the kind words. Regarding Verilog or SystemC, these are quite different. Verilog (or System Verilog) are used for hardware description and cycle accurate logic simulation, while SystemC is usually used for higher level system modeling. While there are packages and so forth that synthesize SystemC, these are not very accepted in industry, as far as I know. Another drawback of using higher level languages is that the gatelevel code is hard to connect to the behavioral description, which makes debugging and ECOs very challenging, if not impossible. So the industry has been very conservative in keeping hardware description at the HDL level and not going too much higher in the stack. One niche approach is Chisel, which was developed as an improved alternative to traditional HDLs, but it has really only caught on with UC Berkeley students and alumni and some others who have mastered it. Another is high level synthesis, which is supported by all the major vendors and can be found in both university and in industry, but despite its maturity, has yet to conquer traditional HDLs and make them irrelevant.