DVD - Kahoot for Lecture 2: Verilog HDL

[@rogerfederer6456]

just curious, why your reset is named rst_ (why the underscore at the end). does it indicate reset to the tool ?

[@AdiTeman]

Hi. No, the tool doesn't "understand" the name of the signal. To the tool, it is just a string. On the other hand, we try to name our signals with meaning and this is one of those examples. In this case, because of the underscore, we can guess or implicitly understand that our reset is active low. In other words, the reset is asserted by pulling rst_ to ground. if we called it "rst" and not "rst_", we could assume that it is active high (i.e., reset is asserted by pulling it to VDD). Other ways you could name an "active low" signal are with an exclamation point (though this is not good practice for computer languages), the word "bar" (e.g., rst_bar), or the letter "b" (e.g., "reset_b" or "resetB"). But, again, these are just strings. You need your code to implement the active low behavior.

[@jaysingh6066]

On latch Inference quiz if we have a synchronous reset that wont be part of sensitivity list. Wanna confirm if your answer was right. Thanks!!

[@AdiTeman]

Hi Jay, I'm not sure I understand what you're asking, but I'll try to respond. In Question 6 (around 14:00 minutes), I show code for a D-Latch with asynchronous low reset. Indeed, if the reset signal was not part of the sensitivity list, then this would be a D-Latch with synchronous reset, as the latch would only reset during the positive phase of the clock. However, in the quiz, all other answers were D-Flip Flops, so there was no option of a D-Latch with synchronous reset... I hope that answered your question. Adi