DVD - Lecture 3c: Library Definition

[@AdiTeman]

Errata: at time 18:25 the output voltage of the High-to-Low level shifter should be VDDL and not VDDH as in the schematic. Thanks @HS_squared for paying attention to this.

[@HS_squared]

Dear professor, In HL level shifter 18:25 , shouldn't the supply be VDDL and output also OUTL?

[@AdiTeman]

That is very true. Interesting that it took so long for someone to point out this mistake :). I've added it to Errata in the pinned comment. Thanks!

[@valentingomez4546]

Which one of your courses covers topics such as diffusion masks, wells, etc?

[@AdiTeman]

These subject are mainly covered in my Digital Integrated Circuits (VLSI) class. Here is a link to the KZbin playlist: kzbin.info/aero/PLZU5hLL_713yF0Lkwjj9O3ttVIuhPV-me

[@meghakg6283]

Great lectures! The link to the slides does not open, does anybody have the slides?

[@AdiTeman]

Thanks! The link isn't available, since the university has blocked access for IPs originating outside of Israel for security purposes. I have uploaded my lecture slide to a sharepoint drive in the meantime, so you can access them here: biu365-my.sharepoint.com/:f:/g/personal/temanad_biu_ac_il/EuORrTC7arlEn3S9M-0q2fEBd5DnUUiMIJ6DFd6cCPl4zw?e=aUktHb

[@meghakg6283]

@@AdiTeman thank you, Professor.

[@AdiTeman]

You're welcome!

[@deevam9756]

Does Standard cells with higher drive strengths occupy two or more standard cell rows??

[@AdiTeman]

No, in almost all cases, they are fit into a single row. There are certain standard cells that may be put into two rows, but these tend to be complex cells, such as level shifters and possibly some flip flops.

[@deevam9756]

@@AdiTeman Thank you sir. @12:04 But you mentioned standard cells with higher drive strengths have larger widths. How is it possible to fit larger width in a single row??

[@mohammed_mairajuddin_musharraf]

How standard cell library is different from PDK? What are contents of Standard cell library and PDK?

[@AdiTeman]

There is actually a fundamental difference. - A process design kit (PDK) is a collection of files that defines the technology process. This includes information, such as the basic components for circuit design (e.g., transistors), the model files for simulating the components (e.g., in SPICE) and the technology file that includes the rules for layout in the technology. The PDK is provided by the FOUNDRY and cannot (or should not) be customized by anyone else. - A standard cell library (SC Lib) or any other IP library is a collection of circuits designed by a circuit designer and not (necessarily) by the foundry. It includes different views of the circuits, as I explain in the video, which enable a digital designer (front end or backend) to integrate these circuits in a digital design flow. A standard cell library is usually provided by an IP vendor and not by the Foundry. In some cases, the foundry provides the SC Lib, but this is just for convenience.

[@venkateshiyer5073]

What does Hard macro mean ? Is hard macro and wrapper same thing ?

[@AdiTeman]

No, not at all. A hard macro is just a block that someone else makes (e.g., an IP vendor or a different design team) that is provided as a black box including layout (GDS). This is as opposed to a soft macro, which is provided as RTL code and you need to synthesize and place and route it yourself.

[@venkateshiyer5073]

@@AdiTeman wow thank you, I'll remember this explanation forever now.