VLSI - Lecture 2b: The Manufacturing Process - Detailed Process Flow

[@vikassh9875]

This makes me so excited and feels like i want to join you in your institute

[@AdiTeman]

Great!

[@babaktorabi313]

Great lectures sir!

[@AdiTeman]

Glad you like them!

[@igorrocha6820]

Thank you a lot for this series, I love the way you explain. What book would you recommend for a beginner in this topic? I just started working on digital implementation and have a high level idea of manufacturing process, but I would like to learn more about the steps you mentioned. Thank you !

[@AdiTeman]

I suggest looking at the list of sources that I put at the end of each lecture (access the slides on my website www.eng.biu.ac.il/temanad/teaching/). I usually write down the main books and lecture series that I used for reference. I must say that I love the Rabaey/Chandrakasan/Borijove text book that mainly focuses on circuit design, but has a good overview of manufacturing process, as well. I learned a lot of the stuff about manufacturing from J. Plummer “Silicon VLSI Technology”, 2000 - especially Chapter 2, even though this is quite an old book. There is a lot of good material on NanoHub, such as Prof. Alam's course, and you have to look at the legendary Prof. Chenming Hu's material on his Berkeley website.

[@igorrocha6820]

What material is used for VIAS ? Why do they have higher resistance ?

[@AdiTeman]

Good question. In very old technologies, they were made with aluminum, similar to the metal interconnect layers. However, as the aspect ratios got larger (higher/thinner contacts and vias), the aluminum wouldn't fill the hole very well, and so tungsten (W) was used. Usually an adhesive layer, such as TiN is filled in first to create a good connection and then the hole is filled with tungsten, and is therefore called a "tungsten plug". Tungsten, however, has higher resistance than Aluminum, and so once copper interconnect was introduced, the Dual Damascene process (overviewed in the lecture) was used to make copper vias. These also have barrier layers to eliminate diffusion from metal to ILD. You can get a good (and much more accurate) explanation here: www.mksinst.com/n/metal-thin-films Regarding resistance - the vias and contacts are very special structures. They tend to be very deep holes (high aspect ratio) filled with material. This is hard to fabricate at such a nanometric scale and so the materials, processes and sizes of the vias are very strictly defined. In the end, you get a thin and long "tunnel" between layers, so you get "many Rsquares" which is high resistance. Plus, this is not entirely through copper, but has to go through higher resistance barrier layers. And finally, in a long conductor, the skin effect makes the current flow around the circumference of the via and so making it bigger, doesn't reduce the resistance as much as putting several vias in parallel.

[@igorrocha6820]

@@AdiTeman Thank you

[@Santoshkumar-lw1gf]

hi prof thanks for ur videos.... jst wanted to knw regarding videos related to www.eng.biu.ac.il/temanad/digital-integrated-circuiessorts/) in he english are recorded..??, which u said u would do .... im looking forward to video as you said video will be better than slide (ur reply to my comment in logic synthesis part1 video)...thanks in advance professor

[@AdiTeman]

Hi Santosh. I'm not sure if you noticed, but indeed, I have started recording these lectures and am updating the webpage and KZbin playlist each time I publish a new lecture (about 1 per week until mid July or so). Enjoy.