Advanced VLSI Design: 2023-24 Lecture 5 Static Timing Analysis

[@manpreetkaurjaswal1175]

One of the best videos seen so far

[@SanjayVidhyadharan]

Thanks a lot

[@johnbollam320]

It is very helpful for placements 🤝 thank u sir

[@SanjayVidhyadharan]

Welcome 👍

[@HakunaMatata0707]

13:20 "Max delay violations are a result of a slow data path, including the registers, tsu therefore it is often called the "Setup" path.". Could someone please explain this statement?

[@SanjayVidhyadharan]

The data needs to reach the input of FF by a time intereval called stup before the arrival of clock. If data arrives slock there will not be adequate setup time

[@30ashishchotani81]

Could you please explain how CRP is 1.4ns at 1:04:24

[@SanjayVidhyadharan]

In the bottom path it is 0.8 X3 = 2.4 and top path is 1+1 = 2ns. Only one path will be active in agice\ven circumstsnce hence CPR = 2.4-1= 1.4 ns

[@rohanyadala9096]

Very nice....

[@SanjayVidhyadharan]

Thanks

[@thnxm8]

woah! thanks a lot!

[@SanjayVidhyadharan]

Thanks a lot

[@anupammathur17]

To calculate Tclk(min) we need to do so by Tclk(min) = tcq+ tlogic+ tsu and if we consider the skew , we subtract del(skew) from the equation. So the Tclk(min) = (6+4+3+3-3-3) = 10n. Hence fmax = 1/10n = 100Mhz. I understand that you directly subtract the slack from Time Period, but iam not able to get that by the general Tclk(min) logic.

[@SanjayVidhyadharan]

Slack is diffenece between T and T min ( if you look at it differenetly). If you let me know the time frame of the video I can undetsnd the querr better and accordingly reply

[@jaywaynes1513]

Hello sir...can you Please creat the playlist for static timing analysis

[@SanjayVidhyadharan]

This is part of my Advanced VLSI Design Course sanjayvidhyadharan.in/courses/advanced-vlsi/

[@bodhi_1083]

Hi Sir, The lecture was really helpful. Where can i get the remaining video for timing constraints of full module. Many thanks in advance!! Sir i have tried to register for your course, but it says user registration is currently not allowed, can you please check.

[@SanjayVidhyadharan]

There is not requirement to register. You can go to the courses page and use the vLSI filter . All courses are freely avalaible to all

[@bodhi_1083]

Thank you sir, i will check