Why Via Impedance Calculators Can Be Inaccurate

[@pavelkobrisev2574]

Awesome explaination! Thank you, Zach!

[@Zachariah-Peterson]

Thank you very much!

[@peterfenwick2540]

Oh my hat! I left PCB manufacture as a process engineer 30 years ago. This was never discussed back then that I can remember and we were making multilayers. Very interesting.

[@VlcAlexx]

Excelent!.. I'm starting routing board with DDR (

[@chromatec-video]

Great video Zach - so when will Altium be offering a proper via impedance calculator - because I could do with one right now!

[@Zachariah-Peterson]

They would need to pull from the Simbeor SDK, honestly Simbeor has the absolute best tool for this... At least Altium is not like certain manufacturers who are putting out via calculators that are totally inaccurate!

[@chromatec-video]

@@Zachariah-Peterson Yes Zach that is very true. A comprehensive via impedance calculator would be a great addition to the Altium signal Integrity toolkit.

[@jebinsatheeshkumar]

Hi Zach, I am a super fan of your videos, I was wondering if it's possible to measure the PCB Trace impedance i.e. 50 ohm using VNA.

[@stephennewberry6876]

Great video, thank you! I love the Simbeor demo - really drives the point home. One question though - if all stitching vias are removed, how does return current flow? How would the result be different if perhaps you have one or two stitching vias far away from the signal? 6 vias is a great approximation of a coaxial structure though :)

[@simbeor]

Stephen, thank you for the feedback on Simbeor. Considering the case with the removed stitching vias, the model in Via Analyzer uses infinite planes - the return current goes through the displacement current between those planes. In 3D EM model, Simbeor 3DML solver is used in Zach's demo - it uses PEC boundary conditions around the simulation area. The via becomes reflective very quickly. If one use Simbeor 3DTF solver and PML boundary conditions, such via will start loosing the energy very quickly. Behavior of the actual via will depend on PCB geometry - it is not a good idea to have such unpredictable dependency. Even use of one stitching via increases the via predictability, two vias increases it further and so on.

[@stephennewberry6876]

@@simbeor Thanks so much for the detailed answer, great info!

[@sto2779]

9:12 - at high signal frequencies, such as 50GHz, it will create a wave at the via line and it is said that it will start to resonate. Can these resonance actually degrade the via and cause it to crack or what not at much higher frequencies? Thanks.

[@Zachariah-Peterson]

You're right that the effect is due to wave propagation, and at certain frequencies there will be constructive interference (a resonance) and destructive interference (anti-resonance) in the region around the via. However there is usually not enough power in practical situations to cause a via to be destroyed. Maybe that will be the case in some applicaiton like power over RF, but those systems should not normally route through vias for multiple reasons and they are normally delivering power at a much lower frequency than the via resonance frequencies.

[@yeso8205]

Seems a bug in Altium: batch editing text frames will make text content all same.