DNI and DNP Designations in PCB Design

[@lawrencemiller3829]

Thanks for a good discussion. I have also seen "NP" for No Populate in schematics drawn by others in Altium Designer. Please consider demonstrating the Altium Designer features, step-by-step, to specify DNI and DNP and the results that inform the PCB fabricators.

[@LightningHelix101]

It’s all fun and games until you accidentally mark your entire schematic DNP

[@AltiumAcademy]

🤣

[@human3444]

Thank you very much .🙏🙏🙏

[@brianernzen2509]

@Zachariah-Peterson Not a layout engineer but I lead board designs on occasion. Im coming from a company that used dxdesigner and output the net list for a layout engineer contractor to do the board. New company uses Altium so I’m trying to understand the design flow and how it relates to various revisions. This video brings to mind some questions i have. I think of the schematic as a reference document that ultimately creates a net list. Once the PCB is created and released, it is a completed part, a subassembly that can be called out by higher level assemblies, generally by PWA(s). At that point if the part population changes, that would roll the revision of the PWA since it would just be a change to the PWA drawing. In the example in the video, changing the schematic would roll the revision of the schematic. Wouldn’t this change the files that lead to the PWB? How in the case of the video in which the schematic is updated do you avoid rolling the revision of the PCB? Thanks for any insight.

[@human3444]

Hello. I had a question, please answer it if possible. This is the question. Is it possible to create a board with lines up to the level of nanometer? If so, how much nanometer do we have? Thanks

[@human3444]

@@richardbekking Hello dear. Thanks for the reply. Sorry I made a mistake, my goal is nanometers. Because I know the technology inside the chip is now nanotechnology, but I forgot that my goal is to get an idea about a harvesting chip, whether it can be printed directly on the board for cheap or not. I apologize again and correct my questions. If you want to delete the answer or correct it, because it is not true, I do not like anyone to read it and it is wrong and to be misled. Thanks

[@Zachariah-Peterson]

​@@human3444 Hi Hassan, today's best semi-additive fabrication technology can reproducibly deposit trace widths down to 25 microns, or 25,000 nanometers. However, there is always motivation to try and get to much smaller trace sizes so that smaller semiconductor packages can be used in PCBs. Hope this helps!

[@human3444]

@@Zachariah-Peterson Thank you very much 🙏🌹

[@chaochang1305]

Use Altium variants，that's the final solution.

[@human3444]

Hello dear .I will try to see what it is .Thank you