Capacitor Self Resonance | Power Integrity in PCB Design

Selecting correct capacitors isn't just a huge component of PCB Design, it's crucial in order to maintain a stable Power Distribution Network (PDN). In this video, Zach Peterson shows you how to do this by breaking down impedance peaks, self-resonant frequency, and more.
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0:00 Intro
0:58 A Sample DC Power Diagram
2:19 High Impedance Peaks
2:58 The Role of Capacitors
3:21 Why Impedance Peaks Occur
4:47 Self-Resonant Frequency
7:01 SPICE Simulations Can Help
7:34 The Value of L
8:34 How to Select the Right Capacitors
8:43 To the Datasheets!
What They do not Teach you About Capacitors: resources.altium.com/p/what-t...
Self-resonant Frequency and High Frequency Capacitor Selection: octopart.com/blog/archives/20...
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[@asmi06]

I always thought ESL means Equivalent Series Inductance. You learn something every day!

[@stephenjbro]

It does. People use effective/equivalent interchangeably here.

[@mauricioextramoney4526]

this serie is amazing! maintain it

[@user-ww2lc1yo9c]

I always find that the videos often somehow leave something to be desired. It would be interesting to see how you choose capacitor values and quantity for a specific PCB case.

[@dmitry.shpakov]

Thank you!

[@sigfreed11]

For those that don’t know, there is a huge difference in impedance (specifically inductance) when you include the full 3D model simulations of a real simulated board

[@Zachariah-Peterson]

Yeah that's true because then you can extract factors like the spreading inductance and real via inductance, but circuit models are a decent way to get started determining the amount of capacitance you would need at different frequency values.

[@user-ss3pn3fi9g]

Очень простой и эффективный урок для начинающих. Но может быть снимите ролик про действительно важные измерения Z для PI и PDN. Сейчас существуют очень дешёвые VNA. 1. с какой стороны измерять импиданс ? - со стороны источника питания - VRM; - со стороны приёмника - DUT; - 2-port измерения от VRM (port 1) до DUT. 2. если рассмотреть шину питания мостового инвертора или однотактного преобразователя, у которого уже есть паразиты в соединениях и транзисторах трансформаторах. 3 если проводить измерения 2-PORT VNA, то как измерить S21 с учётом того, что по сути линия питания имеет паразиты одновременно в двух полюсах и плоскость GND не имеет Z = 0 + J0. Отскок земли будет вносить существенную ошибку и придется применять разделенние GND P1 и GND P2 используя трансформатор или тококомпенсирующий дроссель. Если этого не сделать, то требуется 4PORT VNA , который стоит очень дорого и рассказывать про это тоже можно, но это не будет популярно, хотя и для такого контента найдётся аудитория. 4. Имеет ли смысл ставить последовательно индуктивность или ферритовую бусину.

[@leeslevin7602]

Brilliant, thank you.

[@AltiumAcademy]

You're very welcome!

[@LeandroAguierre]

Great video! This series is very interesting! Please talk about 4 layers PCB (Sig 1 - GND (without split it) - VCC - Sig 2) if it's better or not making a stitching to GND net and cover others layers with new GND copper. So increase the GND area in all the signal layers in addition to the GND plane. Thank!

[@Zachariah-Peterson]

Thanks Leandro, I'll put it in our queue! We have a lot of cool topics coming up so keep watching and learning!

[@AltiumAcademy]

Great suggestion!

[@wborntrager6911]

Got to be a little careful with this, though: Capacitor values that are any where nearby in resonance can interact and create more problems. When more than one value is needed, it may be better to use values that are further apart in resonance and then use several of the same value in parallel to lower the overall curve.

[@LionRelaxe]

I have two books that agree with you, both authors concludes that choosing the highest capacitive value in the smallest package, and placing as many as you can afford will gets you far better result than trying you hands at the "impedance roulette". The left part of the impedance graph is dominated by the capacitance value (more=better), the left half by the package (smaller=better). Placing many in parallels (and close to each other) will lower the whole curve instead of adding peaks here and there. Also, MORE VIAS to the plane. 3 small vias will do a lot for the inductance. See those two very interesting books: PCB Design for Real-World EMI Control, Bruce Archambault, Chapter 8.4 Electromagnetic Compatibility Engineering, Henry W. Ott, Chapter 11.5 to 11.9

[@Zachariah-Peterson]

You brought up the exact point I discussed in another video on controlled ESR capacitors, go check it out if you have time.

[@user-ww2lc1yo9c]

so its not worth having a lot of capacitors in parallel?

[@Zachariah-Peterson]

​ @user-ww2lc1yo9c to reach low PDN impedance values required in large processors up to ~100 MHz range you need to have many small capacitors in parallel. For much smaller ASICs this is not the case because they do not have enough fast I/Os to require large numbers of small capacitors. So in summary, there are practical instances where you need to have many capacitors in parallel, and I think I have shown an example of this in other videos.

[@levtulubjev9018]

nice presentation! Even me stupid understood everything :)

[@AltiumAcademy]

Glad you liked it!

[@bromeliadtotoro7541]

Thank you for the great vid Zach! I was wondering if you could clarify a question I have. With a real bypass capacitor having a self resonant frequency and essentially being an RLC circuit, are there conditions under which it can behave as an oscillator when excited at/near the SRF?

[@Zachariah-Peterson]

Well technically that's exactly what it does when there is a transient event. Whether it behaves like an overdamped, critically damped, or underdamped capacitor depends on the value of its parasitics. Controlled ESR capacitors with high ESR are more likely to be critically damped or overdamped. You can learn more about controlled ESR capacitors here: kzbin.info/www/bejne/eKiTn56crdaHfdk

[@bromeliadtotoro7541]

@@Zachariah-Peterson Thank you for the reply, very helpful! So, if the return path for the capacitor is too long, or the current through the capacitor is large, can bypass capacitors generate a significant amount of radiated noise?

[@samuelburck2381]

Hi, Great video as always! I have a question on selecting these capacitors though. It seems like even though those three fixed values are a myth, why wouldn't someone just pick their own values based on the impedance curves and stick with them forever? Would you want to adjust the values based on the speed of the circuits that are using the PDN? For instance, if I have a 1ns logic signal that uses 3.3V I would want to make sure there is good capacitor impedance overlap in the 1GHz range on the PDN so that when the current is drawn the self resonance is reduced. I guess I am just a bit confused when and why you would want to change the capacitor values except for just wanting a "cleaner" power signal in general

[@Zachariah-Peterson]

Mostly because those regions where those peaks occur and the PDN resonances arise can be at different locations depending on the stackup, sizing of vias back to planes, spreading inductance in the plane layers, pin-package inductance, and the package size of the capacitors you're using. Also if your capacitors are very high Q, then it will be more difficult to pick that value that helps in a lot of designs. Lower Q is usually better for targeting a broad range, but these will have higher impedance so you need more of them in parallel to hit your impedance target. I would say instead of having one capacitor value and sticking with it, find a few capacitor options or ranges and adjust the capacitor value you need based on some simple estimates. For example, if you are workign with a smaller component and you have to use a smaller rail to hit all the power pins, then you might need double the capacitance at your particular frequency.

[@user-ww2lc1yo9c]

@@Zachariah-Peterson how does a person really know what values to use?

[@timpeng1269]

Hi Zach, I heard from Eric Bogatin that the ESL of a capacitor is strongly related to how we mount it on PCB. Does it imply that we cannot just look for impedance curve or inductance value in datasheet since we don’t know how they mount on their test PCB and how they de-embedded? Please share your idea about this.

[@Zachariah-Peterson]

Yes it is true that any pad, trace, and via will add its inductance to the ESL value of a capacitor. There is also spreading inductance to consider in the planes. I would say to be careful when looking at impedance curves, make sure that they are representative of how your capacitor would be mounted or that they provide an inductance value based on case size. AVX has a really good guide on this that lists some values for the self-inductance based on SMD package size: www[dot]avx[dot]com/docs/techinfo/CeramicCapacitors/parasitc.pdf I do like Eric's advice about case size, find the smallest case size that provides the capacitance you need, and you'll have minimized inductance. Then you can worry about how it is mounted; vias connected back to a plane layer may add up to 1 nH to the ESL value, while moderate case sizes would already have about 0.5 to 1 nH ESL. So once you get down to the 0402 or 0201 size caps, so a through-hole via's inductance could comprise a large portion of the total inductance.

[@myetis1990]

Hello, One question that remained non-answered is How we determine the critical frequency which needs to be suppressed for our circuit? For example, let's say my MCU works with a 16mhz OSC, then does it mean I need to select capacitors with almost 16mhz SRF? Or , do I need to select varied capacitors with various SRF including 16Mhz for better noise immunity? I think the second is right but I'm not sure about determining the critical freq as my MCU's OSC freq.

[@user-gn8tr9sr6h]

My guess (this is new to me as well) is that you just follow a logarithmic curve going towards zero, to an infinitely small capacitor. Starting with the frequency you want to filter out.

[@Zachariah-Peterson]

Hi Mustafa, this is a great question as it relates a lot to the difference between switching frequency and bandwidth. I'm going to create an article on the blog about this, and we'll create a corresponding video. Thanks for watching!

[@Zachariah-Peterson]

Hi Mustafa, we looked at part of your question in another video, you can check it out here: kzbin.info/www/bejne/qpOslp6cfstrmqs

[@user-ww2lc1yo9c]

@@Zachariah-Peterson it would be great to create a comprehensive video on this topic and just shoot it down. All relevant information in 1 place.

[@philippguhring1560]

The "Now you can calculate it" at the end sounds like a cliffhanger. Could you give one real practical example how you do that calculation to which parts you actually design in in the end?

[@npurushothaman]

Can you please comment on modelling SMD resistors? How to get the right value of the parasitic capacitance? The vendors do not generally make the resistor models (for use in Altium or ADS) available. Thanks.

[@Zachariah-Peterson]

If it's just a resistor then it's a simple RLC circuit in series. Sometimes you can see the impedance curve from the capacitor datasheet and you can determine the ESL and ESR values from that graph, this is sometimes the case with ceramic caps that are marketed specifically for use high frequency circuits. Some datasheets will specifically list an ESL value, but might only list a maximum ESR value (it varies when not a controlled ESR capacitor). Finally, you could also measure it if you have a good enough scope and square wave generator, probably also with an LCR meter depending on the frequency range where you are looking for the self resonance.

[@npurushothaman]

@@Zachariah-Peterson Sorry, if I am mistaken. You had mentioned capacitor datasheet, ESR and ESL. With SMD caps, yes, we can get the ESL and ESR value and the design kits incorporate these effects. For SMD resistors, there is no such data. For example, if it is wire wound resistor, we would need the inductance value. For SMD resistors, we would need the parallel capacitance value to model them accurately.

[@brentyen3616]

but when u choose different capacitors in parallel, the demo in the video assumes that all 3 ESLs are different..but in general...since their packaging (plus their respective pcb current loops) are most likely the same...seems like put several capacitors hardly lower the total impedence level?

[@Zachariah-Peterson]

They may not have the same total ESL (meaning package ESL + via inductance), they could be different based on package size, where they are located along the PDN, and via inductance. With any impedance generally, if you place N impedances in parallel it lowers the equivalent impedance by (1/N) assuming there are no other parasitics between each impedance.

[@hossammoghrabi1021]

please no music

[@user-ww2lc1yo9c]

yes yes yes

[@bagibadoo439]

There has to be over a hundred jump cuts in this video, please don't edit like that, it makes it very uncomfortable to watch.

[@timpeng1269]

Think capacitors as inductors with DC blocking.